On 2020-11-20 09:09, Vladimir Murzin wrote:
On 11/20/20 8:56 AM, Marc Zyngier wrote:
On 2020-11-20 04:30, Neeraj Upadhyay wrote:
Hi,
For ARM cortex A76, A77, A78 cores (which as per TRM, support AMU)
AA64PFR0[47:44] field is not set, and AMU does not get enabled for
them.
Can you please provide support for these CPUs in cpufeature.c?
If that was the case, that'd be an erratum, and it would need to be
documented as such. It could also be that this is an optional feature
for these cores (though the TRM doesn't suggest that).
Can someone at ARM confirm what is the expected behaviour of these
CPUs?
Not a confirmation, but IIRC, these are imp def features, while our
cpufeatures
catches architected one.
Ah, good point. So these CPUs implement some sort of AMU, and not *the*
AMU.
Yet the register names are the same. Who thought that'd be a good idea?
M.
--
Jazz is not dead. It just smells funny...
