On Wed 28 Oct 02:42 CDT 2020, Manivannan Sadhasivam wrote:
> Add support for clocks maintained by RPMh in SDX55 SoCs.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
> drivers/clk/qcom/clk-rpmh.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index e2c669b08aff..88d010178b59 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -432,6 +432,25 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
> .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
> };
>
> +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
> +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
> +DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0");
> +
> +static struct clk_hw *sdx55_rpmh_clocks[] = {
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_RF_CLK1] = &sdx55_rf_clk1.hw,
> + [RPMH_RF_CLK1_A] = &sdx55_rf_clk1_ao.hw,
> + [RPMH_RF_CLK2] = &sdx55_rf_clk2.hw,
> + [RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw,
> + [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw,
> +};
> +
> +static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
> + .clks = sdx55_rpmh_clocks,
> + .num_clks = ARRAY_SIZE(sdx55_rpmh_clocks),
> +};
> +
> static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
> void *data)
> {
> @@ -519,6 +538,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
> { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
> { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
> { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
> + { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
The sort order is off here.
Regards,
Bjorn
> { }
> };
> MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
> --
> 2.17.1
>
