Hi,
On Mon, Oct 12, 2020 at 2:05 AM Akash Asthana <akashast@xxxxxxxxxxxxxx> wrote:
>
> Hi Stephen,
>
>
> >>
> >> static void geni_se_select_dma_mode(struct geni_se *se)
> >> {
> >> + u32 proto = geni_se_read_proto(se);
> >> u32 val;
> >>
> >> geni_se_irq_clear(se);
> >>
> >> + val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
> >> + if (proto != GENI_SE_UART) {
> > Not a problem with this patch but it would be great if there was a
> > comment here (and probably in geni_se_select_fifo_mode() too) indicating
> > why GENI_SE_UART is special. Is it because GENI_SE_UART doesn't use the
> > main sequencer? I think that is the reason, but I forgot and reading
> > this code doesn't tell me that.
> >
> > Splitting the driver in this way where the logic is in the geni wrapper
> > and in the engine driver leads to this confusion.
>
> GENI_SE_UART uses main sequencer for TX and secondary for RX transfers
> because it is asynchronous in nature.
>
> That's why RX related bits (M_RX_FIFO_WATERMARK_EN |
> M_RX_FIFO_LAST_EN) are not enable in main sequencer for UART.
>
> (M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN) bits are controlled from UART
> driver, it's gets enabled and disabled multiple times from start_tx
> ,stop_tx respectively.
For now I've "solved" this by adding some comments (in the 3rd patch)
basically summarizing what Akash said. I didn't want to go further
than that for now because it felt more important to get the i2c bug
fixed sooner rather than later and re-organizing would be a big enough
change that it'd probably need a few spins.
Our bug trackers don't make it trivially easy to file a public bug
tracking this and assign it to Qualcomm, but I've filed a bug asking
folks at Qualcomm to help with re-organizing things after my patch
series lands. This is internally tracked at Google as b:170766462
("Rejigger geni_se_select_fifo_mode() / geni_se_select_dma_mode() to
not manage interrupt enables").
-Doug
