Re: [PATCH v2 3/3] arm64: dts: Enabled MHI device over PCIe

[gokulsri@xxxxxxxxxxxxxx]

On 2020-08-06 15:56, Manivannan Sadhasivam wrote:
> On Thu, Aug 06, 2020 at 03:02:12PM +0530, Gokul Sriram Palanisamy 
> wrote:
> > Enabled MHI device support over PCIe and added memory
> > reservation required for MHI enabled QCN9000 PCIe card.
>
> There is no DT support exist for MHI as of now, so this is not going to 
> work.
>
> Thanks,
> Mani
Hi Mani,
The dt entries are to be used by the ath11k driver. Will remove 
mhi,max-channels and mhi,timeout
and post a new revision.

Thanks,
Gokul
> > Signed-off-by: Gokul Sriram Palanisamy <gokulsri@xxxxxxxxxxxxxx>
> > ---
> >  arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 58 
> > ++++++++++++++++++++++++++++++
> >  arch/arm64/boot/dts/qcom/ipq8074.dtsi      |  8 +++++
> >  2 files changed, 66 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi 
> > b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> > index 0827055..d201a7b 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> > @@ -24,6 +24,22 @@
> >  		device_type = "memory";
> >  		reg = <0x0 0x40000000 0x0 0x20000000>;
> >  	};
> > +
> > +	reserved-memory {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		qcn9000_pcie0: memory@50f00000 {
> > +			no-map;
> > +			reg = <0x0 0x50f00000 0x0 0x03700000>;
> > +		};
> > +
> > +		qcn9000_pcie1: memory@54600000 {
> > +			no-map;
> > +			reg = <0x0 0x54600000 0x0 0x03700000>;
> > +		};
> > +	};
> >  };
> >
> >  &blsp1_spi1 {
> > @@ -74,3 +90,45 @@
> >  		nand-bus-width = <8>;
> >  	};
> >  };
> > +
> > +&pcie0_rp {
> > +	status = "ok";
> > +
> > +	mhi_0: qcom,mhi@0 {
> > +		reg = <0 0 0 0 0 >;
> > +		qrtr_instance_id = <0x20>;
> > +		#address-cells = <0x2>;
> > +		#size-cells = <0x2>;
> > +
> > +		base-addr = <0x50f00000>;
> > +		qcom,caldb-addr = <0x53E00000>;
> > +		qrtr_node_id = <0x27>;
> > +		mhi,max-channels = <30>;
> > +		mhi,timeout = <10000>;
> > +
> > +		pcie0_mhi: pcie0_mhi {
> > +			status = "ok";
> > +		};
> > +	};
> > +};
> > +
> > +&pcie1_rp {
> > +	status = "ok";
> > +
> > +	mhi_1: qcom,mhi@1 {
> > +		reg = <0 0 0 0 0 >;
> > +		qrtr_instance_id = <0x21>;
> > +		#address-cells = <0x2>;
> > +		#size-cells = <0x2>;
> > +
> > +		base-addr = <0x54600000>;
> > +		qcom,caldb-addr = <0x57500000>;
> > +		qrtr_node_id = <0x28>;
> > +		mhi,max-channels = <30>;
> > +		mhi,timeout = <10000>;
> > +
> > +		pcie1_mhi: pcie1_mhi {
> > +			status = "ok";
> > +		};
> > +	};
> > +};
> > diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
> > b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > index b651345..eef47c1 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> > @@ -709,6 +709,10 @@
> >  				      "ahb",
> >  				      "axi_m_sticky";
> >  			status = "disabled";
> > +
> > +			pcie1_rp: pcie1_rp {
> > +				reg = <0 0 0 0 0>;
> > +			};
> >  		};
> >
> >  		pcie0: pci@20000000 {
> > @@ -779,6 +783,10 @@
> >  				      "axi_m_sticky",
> >  				      "axi_s_sticky";
> >  			status = "disabled";
> > +
> > +			pcie0_rp: pcie0_rp {
> > +				reg = <0 0 0 0 0>;
> > +			};
> >  		};
> >
> >  		tcsr_q6: syscon@1945000 {
> > --
> > 2.7.4