On 16-09-20, 16:11, Stephen Boyd wrote: > This patch series is based on v12 of the msm DP driver submission[1] > plus a compliance patch[2]. In the v5 patch series review I suggested > that the DP PHY and PLL be split out of the drm driver and moved to the > qmp phy driver. This patch series does that, but it is still marked as > an RFC because there are a couple more things to do, mostly updating the > DT binding and getting agreement on how to structure the code. > > Eventually I believe the qmp phy driver will need to listen for type-c > notifiers or somehow know the type-c pinout being used so this driver > can program things slightly differently. Right now, I don't have any way > to test it though, so I've left it as future work. For some more > details, the DP phy and the USB3 phy share the same physical pins on the > SoC and those pins pretty much line up with a type-c pinout modulo some > CC pins for cable orientation detection logic that lives on the PMIC. So > the DP phy can use all four lanes or it can use two lanes and the USB3 > phy can use two lanes. In the hardware designs that I have access to it > is always two lanes for USB3 and two lanes for DP going through what > looks like a type-c pinout so this just hard codes that configuration in > the driver. Applied 1 thru 8, thanks -- ~Vinod
