On Sat, Sep 26, 2020 at 5:52 AM <kholk11@xxxxxxxxx> wrote: > > From: Konrad Dybcio <konradybcio@xxxxxxxxx> > > Port over the command from downstream to prevent undefined > behaviour. > > Signed-off-by: Konrad Dybcio <konradybcio@xxxxxxxxx> > Signed-off-by: AngeloGioacchino Del Regno <kholk11@xxxxxxxxx> > --- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index bdc852e7d979..71cd8a3a6bf1 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -722,6 +722,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) > adreno_is_a512(adreno_gpu)) > gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); > > + /* Disable UCHE global filter as SP can invalidate/flush independently */ > + gpu_write(gpu, 0x00000E81, BIT(29)); Looks like this is REG_A5XX_UCHE_MODE_CNTL? We should define a name for this, rather than open coding. (It's ok if you just add it to a5xx.xml.h, I can push a MR to add this to mesa a5xx.xml) BR, -R > + > /* Enable USE_RETENTION_FLOPS */ > gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); > > -- > 2.28.0 >
