Quoting Sai Prakash Ranjan (2020-09-14 23:55:26) > From: "Isaac J. Manjarres" <isaacm@xxxxxxxxxxxxxx> > > Older chipsets may not be allowed to configure certain LLCC registers > as that is handled by the secure side software. However, this is not > the case for newer chipsets and they must configure these registers > according to the contents of the SCT table, while keeping in mind that > older targets may not have these capabilities. So add support to allow > such configuration of registers to enable capacity based allocation > and power collapse retention for capable chipsets. > > Reason for choosing capacity based allocation rather than the default > way based allocation is because capacity based allocation allows more > finer grain partition and provides more flexibility in configuration. > As for the retention through power collapse, it has an advantage where > the cache hits are more when we wake up from power collapse although > it does burn more power but the exact power numbers are not known at > the moment. > > Signed-off-by: Isaac J. Manjarres <isaacm@xxxxxxxxxxxxxx> > Reviewed-by: Douglas Anderson <dianders@xxxxxxxxxxxx> > [saiprakash.ranjan@xxxxxxxxxxxxxx: use existing config and reword commit msg] > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@xxxxxxxxxxxxxx> > --- Reviewed-by: Stephen Boyd <swboyd@xxxxxxxxxxxx>
