On 9/14/20 7:57 PM, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2020-09-07 07:25:45)
On 04/09/2020 01:26, Jonathan Marek wrote:
Add display clock drivers required to get DSI and DP displays working on
SM8150 and SM8250 SoCs.
Derived from downstream drivers. Notable changes compared to downstream:
- EDP clks removed (nothing uses these even in downstream it seems)
- freq_tbl values for dp_link clk is in Hz and not kHz
On SM8250:
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Can this be carried to v3?
I already included the tag in the last commit which adds the SM8250
dispcc driver (probably should've included it in the SM8250 dt-bindings
patch too though).
