Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8150 SoCs.
Signed-off-by: Jonathan Marek <jonathan@xxxxxxxx>
---
.../bindings/clock/qcom,dispcc.yaml | 10 +--
.../dt-bindings/clock/qcom,dispcc-sm8150.h | 69 +++++++++++++++++++
2 files changed, 75 insertions(+), 4 deletions(-)
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8150.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
index 7d5b25dfe0b1..9702066cda38 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
@@ -11,26 +11,28 @@ maintainers:
description: |
Qualcomm display clock control module which supports the clocks, resets and
- power domains on SDM845/SC7180.
+ power domains on SDM845/SC7180/SM8150.
See also:
dt-bindings/clock/qcom,dispcc-sdm845.h
dt-bindings/clock/qcom,dispcc-sc7180.h
+ dt-bindings/clock/qcom,dispcc-sm8150.h
properties:
compatible:
enum:
- qcom,sdm845-dispcc
- qcom,sc7180-dispcc
+ - qcom,sm8150-dispcc
# NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
# The code had to use hardcoded mechanisms to find the input clocks.
# New dts files should have these clocks.
clocks:
- minItems: 8
+ minItems: 7
items:
- description: Board XO source
- - description: GPLL0 source from GCC
+ - description: GPLL0 source from GCC (sdm845/sc7180 only)
- description: GPLL0 div source from GCC (sdm845 only)
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
@@ -40,7 +42,7 @@ properties:
- description: VCO DIV clock from DP PHY
clock-names:
- minItems: 8
+ minItems: 7
items:
- const: bi_tcxo
- const: gcc_disp_gpll0_clk_src
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8150.h b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
new file mode 100644
index 000000000000..2b96b0b4fe97
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8150_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8150_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK 0
+#define DISP_CC_MDSS_AHB_CLK_SRC 1
+#define DISP_CC_MDSS_BYTE0_CLK 2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
+#define DISP_CC_MDSS_BYTE1_CLK 6
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 7
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 9
+#define DISP_CC_MDSS_DP_AUX1_CLK 10
+#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11
+#define DISP_CC_MDSS_DP_AUX_CLK 12
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13
+#define DISP_CC_MDSS_DP_CRYPTO1_CLK 14
+#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC 15
+#define DISP_CC_MDSS_DP_CRYPTO_CLK 16
+#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 17
+#define DISP_CC_MDSS_DP_LINK1_CLK 18
+#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 19
+#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 20
+#define DISP_CC_MDSS_DP_LINK_CLK 21
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC 22
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK 23
+#define DISP_CC_MDSS_DP_PIXEL1_CLK 24
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 25
+#define DISP_CC_MDSS_DP_PIXEL2_CLK 26
+#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 27
+#define DISP_CC_MDSS_DP_PIXEL_CLK 28
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 29
+#define DISP_CC_MDSS_ESC0_CLK 30
+#define DISP_CC_MDSS_ESC0_CLK_SRC 31
+#define DISP_CC_MDSS_ESC1_CLK 32
+#define DISP_CC_MDSS_ESC1_CLK_SRC 33
+#define DISP_CC_MDSS_MDP_CLK 34
+#define DISP_CC_MDSS_MDP_CLK_SRC 35
+#define DISP_CC_MDSS_MDP_LUT_CLK 36
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 37
+#define DISP_CC_MDSS_PCLK0_CLK 38
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 39
+#define DISP_CC_MDSS_PCLK1_CLK 40
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 41
+#define DISP_CC_MDSS_ROT_CLK 42
+#define DISP_CC_MDSS_ROT_CLK_SRC 43
+#define DISP_CC_MDSS_RSCC_AHB_CLK 44
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 45
+#define DISP_CC_MDSS_VSYNC_CLK 46
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 47
+#define DISP_CC_PLL0 48
+#define DISP_CC_PLL1 49
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_RSCC_BCR 1
+#define DISP_CC_MDSS_SPDM_BCR 2
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+
+#endif
--
2.26.1
