Hi Sivaprakash, On 29-07-20, 12:15, Sivaprakash Murugesan wrote: > > On 7/13/2020 11:25 AM, Vinod Koul wrote: > > On 05-07-20, 14:47, Sivaprakash Murugesan wrote: > > > There were some problem in ipq8074 gen2 pcie phy init sequence, fix > > Can you please describe these problems, it would help review to > > understand the issues and also for future reference to you > > Hi Vinod, > > As you mentioned we are updating few register values > > and also adding clocks and resets. > > the register values are given by the Hardware team and there > > is some fine tuning values are provided by Hardware team for the > > issues we faced downstream. > > Also, few register values are typos for example QSERDES_RX_SIGDET_CNTRL > > is a rx register it was wrongly in serdes table. > > I will try to mention these details in next patch. The right thing to do would be a change per patch explaining the reason. For example, fixing typos in QSERDES_RX_SIGDET_CNTRL, then another to update tuning values based on hw recommendations. Clocks and reset should be different patch This helps us review each change for what it does and helps you down the line to figure why a line of code was changed HTH -- ~Vinod
