Quoting Rob Herring (2020-07-13 08:21:10) > On Fri, Jul 10, 2020 at 05:13:24PM -0700, Stephen Boyd wrote: > > Quoting Loic Poulain (2020-07-03 01:49:43) > > > From: Ilia Lin <ilialin@xxxxxxxxxxxxxx> > > > > > > Each of the CPU clusters (Power and Perf) on msm8996 are > > > clocked via 2 PLLs, a primary and alternate. There are also > > > 2 Mux'es, a primary and secondary all connected together > > > as shown below > > > > > > +-------+ > > > XO | | > > > +------------------>0 | > > > | | > > > PLL/2 | SMUX +----+ > > > +------->1 | | > > > | | | | > > > | +-------+ | +-------+ > > > | +---->0 | > > > | | | > > > +---------------+ | +----------->1 | CPU clk > > > |Primary PLL +----+ PLL_EARLY | | +------> > > > | +------+-----------+ +------>2 PMUX | > > > +---------------+ | | | | > > > | +------+ | +-->3 | > > > +--^+ ACD +-----+ | +-------+ > > > +---------------+ +------+ | > > > |Alt PLL | | > > > | +---------------------------+ > > > +---------------+ PLL_EARLY > > > > > > The primary PLL is what drives the CPU clk, except for times > > > when we are reprogramming the PLL itself (for rate changes) when > > > we temporarily switch to an alternate PLL. A subsequent patch adds > > > support to switch between primary and alternate PLL during rate > > > changes. > > > > > > The primary PLL operates on a single VCO range, between 600MHz > > > and 3GHz. However the CPUs do support OPPs with frequencies > > > between 300MHz and 600MHz. In order to support running the CPUs > > > at those frequencies we end up having to lock the PLL at twice > > > the rate and drive the CPU clk via the PLL/2 output and SMUX. > > > > > > Signed-off-by: Ilia Lin <ilialin@xxxxxxxxxxxxxx> > > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > > > --- > > > > Applied to clk-next > > And this breaks linux-next: > > https://gitlab.com/robherring/linux-dt-bindings/-/jobs/635720095 I guess this is the downside of reviewed-by tags going stale.
