On Thu, Jul 2, 2020 at 9:59 PM Florian Fainelli <f.fainelli@xxxxxxxxx> wrote: > > > > On 7/2/2020 3:29 AM, Robert Marko wrote: > > Some newer SoC-s have a separate MDIO clock that needs to be enabled. > > So lets add support for handling the clocks to the driver. > > > > Signed-off-by: Robert Marko <robert.marko@xxxxxxxxxx> > > --- > > drivers/net/phy/mdio-ipq4019.c | 28 +++++++++++++++++++++++++++- > > 1 file changed, 27 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/net/phy/mdio-ipq4019.c b/drivers/net/phy/mdio-ipq4019.c > > index 0e78830c070b..7660bf006da0 100644 > > --- a/drivers/net/phy/mdio-ipq4019.c > > +++ b/drivers/net/phy/mdio-ipq4019.c > > @@ -9,6 +9,7 @@ > > #include <linux/iopoll.h> > > #include <linux/of_address.h> > > #include <linux/of_mdio.h> > > +#include <linux/clk.h> > > #include <linux/phy.h> > > #include <linux/platform_device.h> > > > > @@ -24,8 +25,12 @@ > > #define IPQ4019_MDIO_TIMEOUT 10000 > > #define IPQ4019_MDIO_SLEEP 10 > > > > +#define QCA_MDIO_CLK_DEFAULT_RATE 100000000 > > 100MHz? Is not that going to be a tad too much for most MDIO devices out > there? This is not the actual MDIO bus clock, that is the clock frequency that SoC clock generator produces. MDIO controller has an internal divider set up for that 100MHz, I don't know the actual MDIO bus clock frequency as it's not listed anywhere. > -- > Florian
