On 7/2/2020 12:18 PM, Robert Marko wrote: > On Thu, Jul 2, 2020 at 3:38 PM Andrew Lunn <andrew@xxxxxxx> wrote: >> >>> + clock-frequency: >>> + default: 100000000 >> >> IEEE 802.3 says the default should be 2.5MHz. Some PHYs will go >> faster, but 100MHz seems unlikely! > This MDIO controller has an internal divider, by default its set for > 100MHz clock. > In IPQ4019 MDIO clock is not controllable but in IPQ6018 etc it's controllable. > That is the only combination I have currently seen used by Qualcomm. Not sure I understand here, the 'clock-frequency' is supposed to denote the MDIO bus output clock frequency, that is the frequency at which all MDIO devices are going to operate at. Is this 100MHz a clock that feeds into the MDIO block and get internally divided by a programmable register to obtain an output MDIO clock? -- Florian
