This patch series is based on v5 of the msm DP driver submission[1]. I
haven't refreshed this to be based on v6, but I can do that soon. In
the v5 patch series review I suggested that the DP PHY and PLL be split
out of the drm driver and moved to the qmp phy driver. This patch series
does that, but it is still marked as an RFC because there are a couple
more things to do, mostly updating the DT binding and getting agreement
on how to structure the code.
Eventually I believe the qmp phy driver will need to listen for type-c
notifiers or somehow know the type-c pinout being used so this driver
can program things slightly differently. Right now, I don't have any way
to test it though, so I've left it as future work. For some more
details, the DP phy and the USB3 phy share the same physical pins on the
SoC and those pins pretty much line up with a type-c pinout modulo some
CC pins for cable orientation detection logic that lives on the PMIC. So
the DP phy can use all four lanes or it can use two lanes and the USB3
phy can use two lanes. In the hardware designs that I have access to it
is always two lanes for USB3 and two lanes for DP going through what
looks like a type-c pinout so this just hard codes that configuration in
the driver.
Here's the example node that I'm using on sc7180:
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>, // usb pll (or serdes)
<0 0x088e8000 0 0x38>, // dp com
<0 0x088ea000 0 0x40>; // dp pll (or serdes)
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x128>, // tx0
<0 0x088e9400 0 0x200>, // rx0
<0 0x088e9c00 0 0x218>, // pcs
<0 0x088e9600 0 0x128>, // tx1
<0 0x088e9800 0 0x200>, // rx1
<0 0x088e9a00 0 0x18>; // pcs misc
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>, // tx0
<0 0x088ea400 0 0x200>, // rx0
<0 0x088eaa00 0 0x200>, // dp phy
<0 0x088ea600 0 0x200>, // tx1
<0 0x088ea800 0 0x200>; // rx1
#clock-cells = <1>;
#phy-cells = <0>;
};
};
I had to put the serdes register region in the wrapper node and jam the
common area (dp_com) in the middle. Sort of a mess but it was the best I
could do to make the driver changes minimially invasive. I also had to
change the node names to 'usb3-phy' and 'dp-phy' from 'phy' so that I
could differentiate the different phys in the driver. Otherwise the qmp
driver was already mostly prepared for two different phys to sit next to
each other inside the phy wrapper so it was mostly just a chore of
moving code from one place to another.
I'll also point out that I found out the DP controller driver is
resetting the aux phy settings right after it configures it. The last
patch in this series rips out the DP PHY and PLL code from the drm
driver and wires in the phy API calls instead. In that same patch I also
fixed this aux reset behavior by removing the bit that resets the aux
phy. I believe that the aux configuration is broken in the DP driver
but I fixed it now I think.
TODO:
* Update DT binding for qmp phy
* Clean up phy power on sequence a bit so that it is done in one place
instead of two
* Allow link rate to change after phy is powered on?
* Make the runtime PM logic detect combo phy and power down both?
Stephen Boyd (8):
phy: qcom-qmp: Move phy mode into struct qmp_phy
phy: qcom-qmp: Remove 'initialized' in favor of 'init_count'
phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'
phy: qcom-qmp: Get dp_com I/O resource by index
phy: qcom-qmp: Add support for DP in USB3+DP combo phy
phy: qcom-qmp: Add support for sc7180 DP phy
clk: qcom: dispcc: Update DP clk ops for phy design
drm/msm/dp: Use qmp phy for DP PLL and PHY
drivers/clk/qcom/clk-rcg2.c | 19 +-
drivers/clk/qcom/dispcc-sc7180.c | 3 -
drivers/gpu/drm/msm/Kconfig | 13 -
drivers/gpu/drm/msm/Makefile | 4 -
drivers/gpu/drm/msm/dp/dp_aux.c | 27 +-
drivers/gpu/drm/msm/dp/dp_aux.h | 6 +-
drivers/gpu/drm/msm/dp/dp_catalog.c | 247 +---
drivers/gpu/drm/msm/dp/dp_catalog.h | 11 +-
drivers/gpu/drm/msm/dp/dp_ctrl.c | 58 +-
drivers/gpu/drm/msm/dp/dp_display.c | 50 +-
drivers/gpu/drm/msm/dp/dp_display.h | 3 -
drivers/gpu/drm/msm/dp/dp_link.c | 2 +
drivers/gpu/drm/msm/dp/dp_panel.c | 1 +
drivers/gpu/drm/msm/dp/dp_parser.c | 123 +-
drivers/gpu/drm/msm/dp/dp_parser.h | 81 +-
drivers/gpu/drm/msm/dp/dp_power.c | 78 +-
drivers/gpu/drm/msm/dp/dp_power.h | 21 -
drivers/gpu/drm/msm/dp/pll/dp_pll.c | 127 --
drivers/gpu/drm/msm/dp/pll/dp_pll.h | 57 -
drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c | 401 ------
drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h | 86 --
drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c | 524 --------
drivers/phy/qualcomm/phy-qcom-qmp.c | 1103 ++++++++++++++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 80 ++
24 files changed, 1133 insertions(+), 1992 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll.c
delete mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll.h
delete mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.c
delete mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm.h
delete mode 100644 drivers/gpu/drm/msm/dp/pll/dp_pll_10nm_util.c
Cc: Jeykumar Sankaran <jsanka@xxxxxxxxxxxxxx>
Cc: Chandan Uddaraju <chandanu@xxxxxxxxxxxxxx>
Cc: Vara Reddy <varar@xxxxxxxxxxxxxx>
Cc: Tanmay Shah <tanmay@xxxxxxxxxxxxxx>
Cc: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
Cc: Manu Gautam <mgautam@xxxxxxxxxxxxxx>
Cc: Sandeep Maheswaram <sanm@xxxxxxxxxxxxxx>
Cc: Douglas Anderson <dianders@xxxxxxxxxxxx>
Cc: Sean Paul <seanpaul@xxxxxxxxxxxx>
[1] https://lore.kernel.org/r/1585701031-28871-1-git-send-email-tanmay@xxxxxxxxxxxxxx
base-commit: 3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162
prerequisite-patch-id: 627a6baa59c072bd77bec81580c3c7ebfafb91f4
prerequisite-patch-id: 867c626c7ad458ceddacc7d47007fda855855ba5
prerequisite-patch-id: b32de781ef4575f6e2811f5d877747e6f517a430
prerequisite-patch-id: 670511d27642902829faf0c5929c829daeeb004c
prerequisite-patch-id: a0db84ff788ba79e4df84642658d3607726fbeef
prerequisite-patch-id: 12421c3c5b640e91613fe780e9d11eb91604f25b
prerequisite-patch-id: 0e064646903933b0e162a44ce392f7a4875116ce
prerequisite-patch-id: b394fb01b5c82db8457311e30403902c445407fd
prerequisite-patch-id: 0770e225225c1b82953a668d0b162ff3191d2955
--
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