On 6/9/20 5:18 AM, Srinivas Kandagatla wrote:
On 09/06/2020 05:34, Vinod Koul wrote:
Hi Jonathan,
On 08-06-20, 16:43, Jonathan Marek wrote:
Adds support for qcom soundwire devices with memory mapped IO registers.
Please use 'SoundWire Master devices' instead :)
Signed-off-by: Jonathan Marek <jonathan@xxxxxxxx>
---
drivers/soundwire/qcom.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index f38d1fd3679f..628747df1c75 100644
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -90,6 +90,7 @@ struct qcom_swrm_ctrl {
struct sdw_bus bus;
struct device *dev;
struct regmap *regmap;
+ void __iomem *mmio;
struct completion *comp;
struct work_struct slave_work;
/* read/write lock */
@@ -154,6 +155,20 @@ static int qcom_swrm_ahb_reg_write(struct
qcom_swrm_ctrl *ctrl,
return SDW_CMD_OK;
}
+static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
+ u32 *val)
+{
+ *val = readl(ctrl->mmio + reg);
+ return SDW_CMD_OK;
+}
+
+static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int
reg,
+ int val)
+{
+ writel(val, ctrl->mmio + reg);
+ return SDW_CMD_OK;
+}
this looks fine but regmap supports mmio also, so I am thinking we
should remove these and set regmap (mmio/slim)... Srini..?
That is doable, but not going to add great value in this case, unless we
are having another layer of abstraction. So keeping it as readl/writel
seems okay to me.
Adding to this, the slim case doesn't use the regmap directly, it goes
through AHB_BRIDGE registers. So using a single regmap path is not
"doable" (at least not in a nice way IMO).
--srini
