On Thu, Apr 30, 2020 at 09:29:47AM +0530, Sharat Masetty wrote:
> This patch adds a new compatible string for sc7180 and also an
> additional clock listing needed to power the TBUs and the TCU.
>
> Signed-off-by: Sharat Masetty <smasetty@xxxxxxxxxxxxxx>
> ---
> v2: Addressed review comments from Doug
>
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index 6515dbe..ba5dba4 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -28,6 +28,7 @@ properties:
> - enum:
> - qcom,msm8996-smmu-v2
> - qcom,msm8998-smmu-v2
> + - qcom,sc7180-smmu-v2
> - qcom,sdm845-smmu-v2
> - const: qcom,smmu-v2
>
> @@ -113,16 +114,23 @@ properties:
> present in such cases.
>
> clock-names:
> + minItems: 2
> + maxItems: 3
> items:
> - const: bus
> - const: iface
> + - const: mem_iface
Hi Sharat -
I think there was a bit of confusion due to renaming between downstream and
upstream. Currently for the sdm845 and friends we have:
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "bus", "iface";
Confusingly these same clocks downstream are "mem_iface_clk" and "iface_clk"
respectively.
It looks like you are trying to add GCC_DDRSS_GPU_AXI_CLK as "mem_iface" which
was formerly "mem_clk" downstream. I'm not sure if the naming change is
intentional or you were trying to make upstream and downstream match and didn't
realize that they were renamed.
I'm not sure if we need DDRSS_GPU_AXI_CLK or not. Empirically it works without
it for sdm845 (I don't have a sc7180 to test) but we should probably loop back
with either the clock team or the hardware designers to be sure there isn't a
corner case that is missing. I agree with Doug that its always best if we don't
need to add a clock.
Jordan
>
> clocks:
> + minItems: 2
> + maxItems: 3
> items:
> - description: bus clock required for downstream bus access and for the
> smmu ptw
> - description: interface clock required to access smmu's registers
> through the TCU's programming interface.
> + - description: clock required for the inner working of SMMU TBUs and the
> + TCU like the pagetable walks and the TLB flushes.
>
> power-domains:
> maxItems: 1
> --
> 1.9.1
>
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