Quoting Bryan O'Donoghue (2020-03-29 05:41:16)
> During the process of debugging a processor derived from the msm8916 which
> we found the new processor was not starting one of its PLLs.
>
> After tracing the addresses and writes that downstream was doing and
> comparing to upstream it became obvious that we were writing to a different
> register location than downstream when trying to configure the PLL.
>
> This error is also present in upstream msm8916.
>
> As an example clk-pll.c::clk_pll_recalc_rate wants to write to
> pll->config_reg updating the bit-field POST_DIV_RATIO. That bit-field is
> defined in PLL_USER_CTL not in PLL_CONFIG_CTL. Taking the BIMC PLL as an
> example
>
> lm80-p0436-13_c_qc_snapdragon_410_processor_hrd.pdf
>
> 0x01823010 GCC_BIMC_PLL_USER_CTL
> 0x01823014 GCC_BIMC_PLL_CONFIG_CTL
>
> This pattern is repeated for gpll0, gpll1, gpll2 and bimc_pll.
>
> This error is likely not apparent since the bootloader will already have
> initialized these PLLs.
>
> This patch corrects the location of config_reg from PLL_CONFIG_CTL to
> PLL_USER_CTL for all relevant PLLs on msm8916.
>
> Fixes commit 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support")
>
> Cc: Georgi Djakov <georgi.djakov@xxxxxxxxxx>
> Cc: Andy Gross <agross@xxxxxxxxxx>
> Cc: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> Cc: Michael Turquette <mturquette@xxxxxxxxxxxx>
> Cc: Stephen Boyd <sboyd@xxxxxxxxxx>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
> ---
Applied to clk-next
