On Thu, Apr 02, 2020 at 02:11:46PM +0200, Ansuel Smith wrote:
> Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset.
> In ipq8064 phy_tx0_term_offset is 7, in rev 2, ipq8065 and other SoC it's
> set to 0 by default.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
> ---
> .../devicetree/bindings/pci/qcom,pcie.txt | 42 +++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> index 6efcef040741..b699f126ea29 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> @@ -5,6 +5,7 @@
> Value type: <stringlist>
> Definition: Value should contain
> - "qcom,pcie-ipq8064" for ipq8064
> + - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
> - "qcom,pcie-apq8064" for apq8064
> - "qcom,pcie-apq8084" for apq8084
> - "qcom,pcie-msm8996" for msm8996 or apq8096
> @@ -295,6 +296,47 @@
> pinctrl-names = "default";
> };
>
> +* Example for ipq8064 rev 2 or ipq8065
Just a new compatible string doesn't warrant a whole new example.
> + pcie@1b500000 {
> + compatible = "qcom,pcie-ipq8064-v2", "snps,dw-pcie";
> + reg = <0x1b500000 0x1000
> + 0x1b502000 0x80
> + 0x1b600000 0x100
> + 0x0ff00000 0x100000>;
> + reg-names = "dbi", "elbi", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
> + 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
> + interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> + clocks = <&gcc PCIE_A_CLK>,
> + <&gcc PCIE_H_CLK>,
> + <&gcc PCIE_PHY_CLK>,
> + <&gcc PCIE_AUX_CLK>,
> + <&gcc PCIE_ALT_REF_CLK>;
> + clock-names = "core", "iface", "phy", "aux", "ref";
> + resets = <&gcc PCIE_ACLK_RESET>,
> + <&gcc PCIE_HCLK_RESET>,
> + <&gcc PCIE_POR_RESET>,
> + <&gcc PCIE_PCI_RESET>,
> + <&gcc PCIE_PHY_RESET>,
> + <&gcc PCIE_EXT_RESET>;
> + reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
> + pinctrl-0 = <&pcie_pins_default>;
> + pinctrl-names = "default";
> + };
> +
> * Example for apq8084
> pcie0@fc520000 {
> compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
> --
> 2.25.1
>
