Quoting Taniya Das (2020-03-27 12:48:02)
> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
> index a250f59..cfe908f 100644
> --- a/drivers/clk/qcom/gdsc.c
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -28,6 +28,7 @@
> /* CFG_GDSCR */
> #define GDSC_POWER_UP_COMPLETE BIT(16)
> #define GDSC_POWER_DOWN_COMPLETE BIT(15)
> +#define GDSC_RETAIN_FF_ENABLE BIT(11)
> #define CFG_GDSCR_OFFSET 0x4
>
> /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
> @@ -202,6 +203,14 @@ static inline void gdsc_assert_reset_aon(struct gdsc *sc)
> regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
> GMEM_RESET_MASK, 0);
> }
> +
> +static inline void gdsc_retain_ff_on(struct gdsc *sc)
Drop inline please.
> +{
> + u32 mask = RETAIN_FF_ENABLE;
Is this supposed to be GDSC_RETAIN_FF_ENABLE?
> +
> + regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
> +}
> +
> static int gdsc_enable(struct generic_pm_domain *domain)
> {
> struct gdsc *sc = domain_to_gdsc(domain);
> @@ -254,6 +263,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)
> udelay(1);
> }
>
> + if (sc->flags & RETAIN_FF_ENABLE)
> + gdsc_retain_ff_on(sc);
> +
> return 0;
> }
>
> diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
> index 64cdc8c..8604d44 100644
> --- a/drivers/clk/qcom/gdsc.h
> +++ b/drivers/clk/qcom/gdsc.h
> @@ -49,6 +49,7 @@ struct gdsc {
> #define AON_RESET BIT(4)
> #define POLL_CFG_GDSCR BIT(5)
> #define ALWAYS_ON BIT(6)
> +#define RETAIN_FF_ENABLE BIT(7)
This is a flag, not a register bit presumably.
> struct reset_controller_dev *rcdev;
> unsigned int *resets;
> unsigned int reset_count;
