Add the additional power domain and the OPP table for ufs on sdm845
so the driver can set the appropriate performance state of the
power domain while setting the clock rate.
Signed-off-by: Rajendra Nayak <rnayak@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 36b9fb1..9a82f78 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1803,6 +1803,21 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ufs_opp_table: ufs-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ };
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
@@ -1811,7 +1826,8 @@
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
- power-domains = <&gcc UFS_PHY_GDSC>;
+ power-domains = <&gcc UFS_PHY_GDSC>, <&rpmhpd SDM845_CX>;
+ power-domain-names = "gdsc_pd", "rpmh_pd";
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
@@ -1836,6 +1852,9 @@
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+
+ operating-points-v2 = <&ufs_opp_table>;
+
freq-table-hz =
<50000000 200000000>,
<0 0>,
--
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