On 02-04-20, 19:23, Wesley Cheng wrote:
> This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs. There
> are potentially multiple instances of this UTMI PHY on the
> SOC, all which can utilize this driver. The V2 driver will
> have a different register map compared to V1.
Some nitpicks below, otherwise:
Reviewed-by: Vinod Koul <vkoul@xxxxxxxxxx>
> +/**
> + * struct qcom_snps_hsphy - structure holding snps hs phy attributes
> + *
> + * @phy: generic phy
> + * @base: iomapped memory space for qubs2 phy
> + *
> + * @cfg_ahb_clk: AHB2PHY interface clock
> + * @ref_clk: phy reference clock
> + * @iface_clk: phy interface clock
> + * @phy_reset: phy reset control
> + * @vregs: regulator supplies bulk data
> +
This is missing the marker * for kernel doc
> + * @phy_initialized: if PHY has been initialized correctly
> + *
This empty line is redundant
> + */
> +struct qcom_snps_hsphy {
> + struct phy *phy;
> + void __iomem *base;
> +
> + struct clk *cfg_ahb_clk;
> + struct clk *ref_clk;
> + struct reset_control *phy_reset;
> + struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];
> +
> + bool phy_initialized;
> +};
> +
> +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
> + u32 mask, u32 val)
coding style mandates that second line should start at preceeding line
opening brace :), so can you please make it:
static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
u32 mask, u32 val)
--
~Vinod
