On Fri 27 Mar 15:32 PDT 2020, Ansuel Smith wrote:
> From: Ajay Kishore <akisho@xxxxxxxxxxxxxx>
>
> For IPQ806x targets, TZ protects the registers that are used to
> configure the routing of interrupts to a target processor.
> To resolve this, this patch uses scm call to route GPIO interrupts
> to application processor. Also the scm call interface is changed.
>
> Signed-off-by: Ajay Kishore <akisho@xxxxxxxxxxxxxx>
> Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
Thanks,
Bjorn
> ---
> v3:
> * Rename route_to_apps to intr_target_use_scm
> * Follow standard design and rename base_reg to phys_base
> * Add additional comments in route interrupts condition
>
> v2:
> * Move static varibale in msm_pinctrl struct
> * Revert '4b024225c4a8 ("pinctrl: use devm_platform_ioremap_resource() to simplify code")'
> to get base_reg addr
>
> drivers/pinctrl/qcom/pinctrl-msm.c | 42 +++++++++++++++++++++++++-----
> 1 file changed, 36 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 9a8daa256a32..7d2a34beb1b6 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -22,6 +22,8 @@
> #include <linux/reboot.h>
> #include <linux/pm.h>
> #include <linux/log2.h>
> +#include <linux/qcom_scm.h>
> +#include <linux/io.h>
>
> #include <linux/soc/qcom/irq.h>
>
> @@ -60,6 +62,8 @@ struct msm_pinctrl {
> struct irq_chip irq_chip;
> int irq;
>
> + bool intr_target_use_scm;
> +
> raw_spinlock_t lock;
>
> DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
> @@ -68,6 +72,7 @@ struct msm_pinctrl {
>
> const struct msm_pinctrl_soc_data *soc;
> void __iomem *regs[MAX_NR_TILES];
> + u32 phys_base[MAX_NR_TILES];
> };
>
> #define MSM_ACCESSOR(name) \
> @@ -882,11 +887,31 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
> else
> clear_bit(d->hwirq, pctrl->dual_edge_irqs);
>
> - /* Route interrupts to application cpu */
> - val = msm_readl_intr_target(pctrl, g);
> - val &= ~(7 << g->intr_target_bit);
> - val |= g->intr_target_kpss_val << g->intr_target_bit;
> - msm_writel_intr_target(val, pctrl, g);
> + /* Route interrupts to application cpu.
> + * With intr_target_use_scm interrupts are routed to
> + * application cpu using scm calls.
> + */
> + if (pctrl->intr_target_use_scm) {
> + u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
> + int ret;
> +
> + qcom_scm_io_readl(addr, &val);
> +
> + val &= ~(7 << g->intr_target_bit);
> + val |= g->intr_target_kpss_val << g->intr_target_bit;
> +
> + ret = qcom_scm_io_writel(addr, val);
> + if (ret)
> + dev_err(pctrl->dev,
> + "Failed routing %lu interrupt to Apps proc",
> + d->hwirq);
> + }
> + } else {
> + val = msm_readl_intr_target(pctrl, g);
> + val &= ~(7 << g->intr_target_bit);
> + val |= g->intr_target_kpss_val << g->intr_target_bit;
> + msm_writel_intr_target(val, pctrl, g);
> + }
>
> /* Update configuration for gpio.
> * RAW_STATUS_EN is left on for all gpio irqs. Due to the
> @@ -1241,6 +1266,9 @@ int msm_pinctrl_probe(struct platform_device *pdev,
> pctrl->dev = &pdev->dev;
> pctrl->soc = soc_data;
> pctrl->chip = msm_gpio_template;
> + pctrl->intr_target_use_scm = of_device_is_compatible(
> + pctrl->dev->of_node,
> + "qcom,ipq8064-pinctrl");
>
> raw_spin_lock_init(&pctrl->lock);
>
> @@ -1253,9 +1280,12 @@ int msm_pinctrl_probe(struct platform_device *pdev,
> return PTR_ERR(pctrl->regs[i]);
> }
> } else {
> - pctrl->regs[0] = devm_platform_ioremap_resource(pdev, 0);
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(pctrl->regs[0]))
> return PTR_ERR(pctrl->regs[0]);
> +
> + pctrl->phys_base[0] = res->start;
> }
>
> msm_pinctrl_setup_pm_reset(pctrl);
> --
> 2.25.1
>
