On 2020-03-12 11:33, Maulik Shah wrote:
On 2/27/2020 6:39 AM, Marc Zyngier wrote:Maulik, I'd appreciate if you could Cc me on all irqchip patches.Sure Marc, i kept you in Cc for V2 addressing stephen's comments.
Thanks. Make sure you use maz@xxxxxxxxxx (I accidentally replied from my personal address).
On 2020-02-25 17:16, Stephen Boyd wrote:Quoting Maulik Shah (2020-02-21 03:20:59)On 2/20/2020 7:51 AM, Stephen Boyd wrote:How are wakeups supposed to work when the CPU cluster power is disabled in low power CPU idle modes? Presumably the parent irq controller is powered off (in this case it's an ARM GIC) and we would need to have the interrupt be "enabled" or "unmasked" at the PDC for the irq to wakeupthe cluster.Correct. Interrupt needs to be "enabled" or "unmasked" at wakeup capable PDC for irqchip to wakeup from "deep" low power modes where parent GIC may not bemonitoring interrupt and only PDC is monitoring.these "deep" low power modes can either be triggered by kernel "suspend" or "cpuidle" path for which drivers may or may not have registered for suspend or cpu/cluster pm notifications to make a decision of enabling wakeup capability.Loosing interrupt delivery in idle is not an acceptable behaviour. Idle != suspend.Agree, we are not lossing it, but rather RFC v1 was keeping a requirement on drivers to keep wake enabled by calling irq_set_wake when the interrupt is routed via PDC, even after coming out of suspend.
An endpoint driver shouldn't have to know what interrupt controller it
is connected to. So your "when the interrupt is routed via PDC" is
not enforceable.
M.
--
Jazz is not dead. It just smells funny...
