I've had looked this too, and please ignore my sob, and feel free to add my r-b.
Reviewed-by: Robert Foss <robert.foss@xxxxxxxxxx>
On Wed, 4 Mar 2020 at 20:08, Robert Foss <robert.foss@xxxxxxxxxx> wrote:
>
> Due to lack of suitable hardware, I currently can't test the msm8916,
> but I have written similar DT nodes for the sdm845, which indeed work properly.
>
> Signed-off-by: Robert Foss <robert.foss@xxxxxxxxxx>
>
> On Wed, 4 Mar 2020 at 17:49, Loic Poulain <loic.poulain@xxxxxxxxxx> wrote:
> >
> > The msm8916 CCI controller provides one CCI/I2C bus.
> >
> > Signed-off-by: Loic Poulain <loic.poulain@xxxxxxxxxx>
> > ---
> > v2: add this patch in the series
> > v3: add only cci node for now
> >
> > arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> > index 8686e10..985cb5f 100644
> > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> > @@ -1451,6 +1451,33 @@
> > };
> > };
> >
> > + cci@1b0c000 {
> > + compatible = "qcom,msm8916-cci";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x1b0c000 0x1000>;
> > + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
> > + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
> > + <&gcc GCC_CAMSS_CCI_AHB_CLK>,
> > + <&gcc GCC_CAMSS_CCI_CLK>,
> > + <&gcc GCC_CAMSS_AHB_CLK>;
> > + clock-names = "camss_top_ahb", "cci_ahb",
> > + "cci", "camss_ahb";
> > + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
> > + <&gcc GCC_CAMSS_CCI_CLK>;
> > + assigned-clock-rates = <80000000>, <19200000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&cci0_default>;
> > + status = "disabled";
> > +
> > + cci0: i2c-bus@0 {
> > + reg = <0>;
> > + clock-frequency = <400000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > +
> > camss: camss@1b00000 {
> > compatible = "qcom,msm8916-camss";
> > reg = <0x1b0ac00 0x200>,
> > --
> > 2.7.4
> >
