On Thu 20 Feb 01:20 PST 2020, Sayali Lokhande wrote: > During GCC level clock gating of MCLK, the async FIFO > gets into some hang condition, such that for the next > transfer after MCLK ungating, first bit of CMD response > doesn't get written in to the FIFO. This cause the CPSM > to hang eventually leading to SW timeout. > > To fix the issue, toggle the FIFO write clock after > MCLK ungated to get the FIFO pointers and flags to > valid states. > Please don't provide cover letters for a single patch. Regards, Bjorn > Ram Prakash Gupta (1): > mmc: sdhci-msm: Toggle fifo write clk after ungating sdcc clk > > drivers/mmc/host/sdhci-msm.c | 43 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project
