Hi Bjorn,
+ interconnects = <&qup_virt MASTER_QUP_CORE_0
+ &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC
+ &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0
+ &mc_virt SLAVE_EBI1>;
Please ignore the 80-char "limit" and write this as:
interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
<&gem_noc ...>,
<&aggre1_noc ...>;
Regards,
Bjorn
ok
Regards,
Akash
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