In the new world input clocks should be matched by ".fw_name". sc7180
is new enough that no backward compatibility use of global names
should be needed. Remove it.
With a proper device tree and downstream display patches I have
verified booting a sc7180 up and seeing the display after this patch.
Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC7180")
Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
---
Changes in v4: None
Changes in v3:
- Patch ("clk: qcom: Get rid of fallback...dispcc-sc7180") split out for v3.
- Unlike in v2, use internal name instead of purist name.
Changes in v2: None
drivers/clk/qcom/dispcc-sc7180.c | 23 ++++++++++-------------
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c
index 30c1e25d3edb..a820e1558677 100644
--- a/drivers/clk/qcom/dispcc-sc7180.c
+++ b/drivers/clk/qcom/dispcc-sc7180.c
@@ -81,7 +81,7 @@ static const struct parent_map disp_cc_parent_map_0[] = {
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+ { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_1[] = {
@@ -93,10 +93,9 @@ static const struct parent_map disp_cc_parent_map_1[] = {
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
- { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" },
- { .fw_name = "dp_phy_pll_vco_div_clk",
- .name = "dp_phy_pll_vco_div_clk"},
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+ { .fw_name = "dp_phy_pll_link_clk" },
+ { .fw_name = "dp_phy_pll_vco_div_clk" },
+ { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_2[] = {
@@ -107,9 +106,8 @@ static const struct parent_map disp_cc_parent_map_2[] = {
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
- { .fw_name = "dsi0_phy_pll_out_byteclk",
- .name = "dsi0_phy_pll_out_byteclk" },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+ { .fw_name = "dsi0_phy_pll_out_byteclk" },
+ { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
@@ -125,7 +123,7 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .hw = &disp_cc_pll0.clkr.hw },
{ .fw_name = "gcc_disp_gpll0_clk_src" },
{ .hw = &disp_cc_pll0_out_even.clkr.hw },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+ { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_4[] = {
@@ -137,7 +135,7 @@ static const struct parent_map disp_cc_parent_map_4[] = {
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "gcc_disp_gpll0_clk_src" },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+ { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
@@ -148,9 +146,8 @@ static const struct parent_map disp_cc_parent_map_5[] = {
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
- { .fw_name = "dsi0_phy_pll_out_dsiclk",
- .name = "dsi0_phy_pll_out_dsiclk" },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+ { .fw_name = "dsi0_phy_pll_out_dsiclk" },
+ { .fw_name = "core_bi_pll_test_se" },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
--
2.25.0.341.g760bfbb309-goog
