The qcom,dispcc bindings had a few problems with them:
1. They didn't specify all the clocks that dispcc is a client of.
Specifically on sc7180 there are two clocks from the DSI PHY and
two from the DP PHY. On sdm845 there are actually two DSI PHYs
(each of which has two clocks). These all need to be specified.
2. The sdm845.dtsi has existed for quite some time without specifying
the clocks. The Linux driver was relying on global names to match
things up. While we should transition things, it should be noted
in the bindings.
NOTE: It may be slightly controversial that I didn't re-order the
clocks and name the "DSI" clocks on sc7180 to "dsi0". That would have
allowed me to have a single table and just use minItems/maxItems to
specify that sc7180 only had one DSI PHY. I almost did that, but it
felt a little weird. Why did the DSI clock have a 0 but not the DP
clock? If we add a SoC that has a 2nd DP port then we can't
retroactively name old ones. What if we have a SoC that has HDMI but
only one DSI lane? It felt cleaner to me to just duplicate.
Also note that I updated the example.
Fixes: 5d28e44ba630 ("dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings")
Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
---
Changes in v2:
- Patch ("dt-bindings: clock: Fix qcom,dispcc...") new for v2.
.../bindings/clock/qcom,dispcc.yaml | 87 +++++++++++++++----
1 file changed, 71 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
index 9c58e02a1de1..560c52ce3da5 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
@@ -19,18 +19,6 @@ properties:
- qcom,sc7180-dispcc
- qcom,sdm845-dispcc
- clocks:
- minItems: 1
- maxItems: 2
- items:
- - description: Board XO source
- - description: GPLL0 source from GCC
-
- clock-names:
- items:
- - const: xo
- - const: gpll0
-
'#clock-cells':
const: 1
@@ -52,16 +40,83 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sc7180-dispcc
+then:
+ properties:
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 source from GCC
+ - description: Byte clock from DSI PHY
+ - description: Pixel clock from DSI PHY
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ clock-names:
+ items:
+ - const: xo
+ - const: gpll0
+ - const: dsi_phy_pll_byte
+ - const: dsi_phy_pll_pixel
+ - const: dp_phy_pll_link
+ - const: dp_phy_pll_vco_div
+
+else:
+ if:
+ # NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
+ # The code had to use hardcoded mechanisms to find the input clocks.
+ # Any sdm845 device trees should be transitioned, but actual code may
+ # need to handle old dts files.
+ properties:
+ compatible:
+ contains:
+ const: qcom,sdm845-dispcc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 source from GCC
+ - description: Byte clock from DSI PHY0
+ - description: Pixel clock from DSI PHY0
+ - description: Byte clock from DSI PHY1
+ - description: Pixel clock from DSI PHY1
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ clock-names:
+ items:
+ - const: xo
+ - const: gpll0
+ - const: dsi0_phy_pll_byte
+ - const: dsi0_phy_pll_pixel
+ - const: dsi1_phy_pll_byte
+ - const: dsi1_phy_pll_pixel
+ - const: dp_phy_pll_link
+ - const: dp_phy_pll_vco_div
+
examples:
# Example of DISPCC with clock node properties for SDM845:
- |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
- reg = <0xaf00000 0x10000>;
- clocks = <&rpmhcc 0>, <&gcc 24>;
- clock-names = "xo", "gpll0";
+ reg = <0 0x0af00000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <&dsi0_phy 0>, <&dsi0_phy 1>,
+ <&dsi1_phy 0>, <&dsi1_phy 1>,
+ <&dp_phy 0>, <&dp_phy 1>;
+ clock-names = "xo", "gpll0",
+ "dsi0_phy_pll_byte", "dsi0_phy_pll_pixel",
+ "dsi1_phy_pll_byte", "dsi1_phy_pll_pixel",
+ "dp_phy_pll_link", "dp_phy_pll_vco_div";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- };
+ };
...
--
2.25.0.341.g760bfbb309-goog
