On 1/23/2020 5:00 AM, Manivannan Sadhasivam wrote:
Hi Arnd,
On Thu, Jan 23, 2020 at 12:39:06PM +0100, Arnd Bergmann wrote:
On Thu, Jan 23, 2020 at 12:19 PM Manivannan Sadhasivam
<manivannan.sadhasivam@xxxxxxxxxx> wrote:
+int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl,
+ void __iomem *base, u32 offset, u32 *out)
+{
+ u32 tmp = readl_relaxed(base + offset);
....
+void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
+ u32 offset, u32 val)
+{
+ writel_relaxed(val, base + offset);
Please avoid using _relaxed accessors by default, and use the regular
ones instead. There are a number of things that can go wrong with
the relaxed version, so ideally each caller should have a comment
explaining why this instance is safe without the barriers and why it
matters to not have it.
If there are performance critical callers of mhi_read_reg/mhi_write_reg,
you could add mhi_read_reg_relaxed/mhi_write_reg_relaxed for those
and apply the same rules there.
Usually most mmio accesses are only needed for reconfiguration or
other slow paths.
Fair point. I'll defer to readl/writel APIs and I also need to add
le32_to_cpu/cpu_to_le32 to them.
I would expect we would be using these in the "hot" path.
I'm a bit confused, I thought the convention was to put a comment why a
barrier was necessary, now we should be putting a comment why a barrier
is not necessary?
--
Jeffrey Hugo
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
