From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@xxxxxxxxxx> Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed phy controller embedded in QCS404. Based on Sriharsha Allenki's <sallenki@xxxxxxxxxxxxxx> original definitions. [bod: converted to yaml format] Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@xxxxxxxxxx> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@xxxxxxxxx> Cc: Rob Herring <robh+dt@xxxxxxxxxx> Cc: Mark Rutland <mark.rutland@xxxxxxx> Cc: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@xxxxxxxxx> Cc: devicetree@xxxxxxxxxxxxxxx Cc: linux-kernel@xxxxxxxxxxxxxxx Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx> --- .../bindings/phy/intel,lgm-emmc-phy.yaml | 56 -------------- .../devicetree/bindings/phy/qcom,usb-ss.yaml | 75 +++++++++++++++++++ 2 files changed, 75 insertions(+), 56 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml deleted file mode 100644 index ff7959c21af0..000000000000 --- a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml +++ /dev/null @@ -1,56 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings - -maintainers: - - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> - -description: |+ - Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon - node is used to reference the base address of eMMC phy registers. - - The eMMC PHY node should be the child of a syscon node with the - required property: - - - compatible: Should be one of the following: - "intel,lgm-syscon", "syscon" - - reg: - maxItems: 1 - -properties: - compatible: - const: intel,lgm-emmc-phy - - "#phy-cells": - const: 0 - - reg: - maxItems: 1 - - clocks: - maxItems: 1 - -required: - - "#phy-cells" - - compatible - - reg - - clocks - -examples: - - | - sysconf: chiptop@e0200000 { - compatible = "intel,lgm-syscon", "syscon"; - reg = <0xe0200000 0x100>; - - emmc-phy: emmc-phy@a8 { - compatible = "intel,lgm-emmc-phy"; - reg = <0x00a8 0x10>; - clocks = <&emmc>; - #phy-cells = <0>; - }; - }; -... diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml new file mode 100644 index 000000000000..3325b2f2e6a8 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#"; +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; + +title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY + +maintainers: + - Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx> + +description: | + Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY + +properties: + compatible: + enum: + - qcom,usb-ssphy + + reg: + maxItems: 1 + description: USB PHY base address and length of the register map. + + "#phy-cells": + const: 0 + description: Should be 0. See phy/phy-bindings.txt for details. + + clocks: + maxItems: 3 + minItems: 3 + description: phandles for rpmcc clock, PHY AHB clock, SuperSpeed pipe clock. + + clock-names: + items: + - const: ref + - const: phy + - const: pipe + + vdd-supply: + maxItems: 1 + description: phandle to the regulator VDD supply node. + + vdda1p8-supply: + maxItems: 1 + description: phandle to the regulator 1.8V supply node. + + resets: + items: + - description: COM reset + - description: PHY reset line + + reset-names: + items: + - const: com + - const: phy + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-qcs404.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + usb3_phy: usb3-phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x78000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "phy", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + }; +... -- 2.25.0
