Some hardware variants contain a system level cache or the last level cache(llc). This cache is typically a large block which is shared by multiple clients on the SOC. GPU uses the system cache to cache both the GPU data buffers(like textures) as well the SMMU pagetables. This helps with improved render performance as well as lower power consumption by reducing the bus traffic to the system memory. The system cache architecture allows the cache to be split into slices which then be used by multiple SOC clients. This patch series is an effort to enable and use two of those slices perallocated for the GPU, one for the GPU data buffers and another for the GPU SMMU hardware pagetables. To enable the system cache driver, add [1] to your stack if not already present. Please review. [1] https://lore.kernel.org/patchwork/patch/1165298/ Jordan Crouse (1): iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context Sharat Masetty (3): drm/msm: rearrange the gpu_rmw() function drm/msm: Pass mmu features to generic layers drm/msm/a6xx: Add support for using system cache(LLC) Vivek Gautam (1): iommu/arm-smmu: Add domain attribute for QCOM system cache drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 122 +++++++++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 +++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- drivers/gpu/drm/msm/msm_drv.c | 8 +++ drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_gpu.c | 6 +- drivers/gpu/drm/msm/msm_gpu.h | 6 +- drivers/gpu/drm/msm/msm_iommu.c | 13 ++++ drivers/gpu/drm/msm/msm_mmu.h | 14 ++++ drivers/iommu/arm-smmu-impl.c | 3 +- drivers/iommu/arm-smmu-qcom.c | 10 +++ drivers/iommu/arm-smmu.c | 25 +++++-- drivers/iommu/arm-smmu.h | 4 +- include/linux/iommu.h | 1 + 19 files changed, 216 insertions(+), 20 deletions(-) -- 1.9.1
