Hi, On Fri, Dec 13, 2019 at 4:07 PM Daniel Vetter <daniel@xxxxxxxx> wrote: > > On Fri, Dec 13, 2019 at 03:45:30PM -0800, Douglas Anderson wrote: > > The bridge chip supports these DP rates according to TI's spec: > > * 1.62 Gbps (RBR) > > * 2.16 Gbps > > * 2.43 Gbps > > * 2.7 Gbps (HBR) > > * 3.24 Gbps > > * 4.32 Gbps > > * 5.4 Gbps (HBR2) > > > > As far as I can tell, only RBR, HBR, and HBR2 are part of the DP spec. > > If other rates work then I believe it's because the sink has allowed > > bending the spec a little bit. > > I think you need to look at the eDP spec. And filter this stuff correctly > (there's more fields there for these somewhat irky edp timings). Simply > not using them works, but it's defeating the point of having these > intermediate clocks for edp panels. Ah, I see my problem. I had earlier only found the eDP 1.3 spec which doesn't mention these rates. The eDP 1.4 spec does, however. ...and the change log for 1.4 specifically mentions that it added 4 new link rates and also adds the "SUPPORTED_LINK_RATES" register. I can try to spin a v2 but for now I'll hold off for additional feedback. I'll also note that I'd be totally OK if just the first 8 patches in this series landed for now and someone could eventually figure out how to make this work. With just the first 8 patches I think we will still be in an improved state compared to where we were before (and it fixes the panel I care about) and someone could later write the code to skip unsupported rates... -Doug
