The qspi pinctrl nodes had the wrong intentation and sort ordering and
the main qspi node was placed down in the pinctrl section. Fix.
Fixes: ba3fc6496366 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1")
Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 73 +++++++++++++------------
1 file changed, 37 insertions(+), 36 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 189254f5ae95..5eab3a282eba 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -232,6 +232,20 @@ vreg_bob: bob {
};
};
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -250,6 +264,29 @@ &uart8 {
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
+&qspi_clk {
+ pinconf {
+ pins = "gpio63";
+ bias-disable;
+ };
+};
+
+&qspi_cs0 {
+ pinconf {
+ pins = "gpio68";
+ bias-disable;
+ };
+};
+
+&qspi_data01 {
+ pinconf {
+ pins = "gpio64", "gpio65";
+
+ /* High-Z when no transfers; nice to park the lines */
+ bias-pull-up;
+ };
+};
+
&qup_i2c2_default {
pinconf {
pins = "gpio15", "gpio16";
@@ -364,39 +401,3 @@ pinconf {
};
};
-&qspi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <25000000>;
- spi-tx-bus-width = <2>;
- spi-rx-bus-width = <2>;
- };
-};
-
-&qspi_cs0 {
- pinconf {
- pins = "gpio68";
- bias-disable;
- };
-};
-
-&qspi_clk {
- pinconf {
- pins = "gpio63";
- bias-disable;
- };
-};
-
-&qspi_data01 {
- pinconf {
- pins = "gpio64", "gpio65";
-
- /* High-Z when no transfers; nice to park the lines */
- bias-pull-up;
- };
-};
--
2.24.0.525.g8f36a354ae-goog
