Re: [PATCH 1/6] clk: qcom: Drop gcc_aggre1_pnoc_ahb_clk clock

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This patch of mine was more of a stopgap fix. Adding Rajendra, who
authored "clk: qcom: Add some missing gcc clks for msm8996", for
review.

On Thu, 5 Dec 2019 at 21:45, Paolo Pisati <p.pisati@xxxxxxxxx> wrote:
>
> From: Amit Pundir <amit.pundir@xxxxxxxxxx>
>
> Clock "gcc_aggre1_pnoc_ahb_clk" added in QcomLT commit 9a108d744fda
> ("clk: qcom: Add some missing gcc clks for msm8996"), broke USB
> gagdets for db820c. So drop it for now and re-visit the dropped
> changes while submitting it upstream.
>
> Fixes: 9a108d744fda ("clk: qcom: Add some missing gcc clks for msm8996")

Also this ^^ is not upstream commit. Upstream commit is:
b567752144e3 ("clk: qcom: Add some missing gcc clks for msm8996")

Regards,
Amit Pundir

> Signed-off-by: Amit Pundir <amit.pundir@xxxxxxxxxx>
> ---
>  drivers/clk/qcom/gcc-msm8996.c | 15 ---------------
>  1 file changed, 15 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> index d004cda..c1e1148 100644
> --- a/drivers/clk/qcom/gcc-msm8996.c
> +++ b/drivers/clk/qcom/gcc-msm8996.c
> @@ -2937,20 +2937,6 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
>         },
>  };
>
> -static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
> -       .halt_reg = 0x82014,
> -       .clkr = {
> -               .enable_reg = 0x82014,
> -               .enable_mask = BIT(0),
> -               .hw.init = &(struct clk_init_data){
> -                       .name = "gcc_aggre1_pnoc_ahb_clk",
> -                       .parent_names = (const char *[]){ "periph_noc_clk_src" },
> -                       .num_parents = 1,
> -                       .ops = &clk_branch2_ops,
> -               },
> -       },
> -};
> -
>  static struct clk_branch gcc_aggre2_ufs_axi_clk = {
>         .halt_reg = 0x83014,
>         .clkr = {
> @@ -3453,7 +3439,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
>         [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
>         [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
>         [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
> -       [GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
>         [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
>         [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
>         [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
> --
> 2.7.4
>



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