On Tue, Oct 29, 2019 at 05:44:27PM +0100, Ulf Hansson wrote: > Update PSCI DT bindings to allow to represent idle states for CPUs and the > CPU topology, by using a hierarchical layout. Primarily this is done by > re-using the existing DT bindings for PM domains [1] and for PM domain idle > states [2]. > > Let's also add an example into the document for the PSCI DT bindings, to > clearly show the new hierarchical based layout. The currently supported > flattened layout, is already described in the ARM idle states bindings [3], > so let's leave that as is. > > [1] Documentation/devicetree/bindings/power/power_domain.txt > [2] Documentation/devicetree/bindings/power/domain-idle-state.txt > [3] Documentation/devicetree/bindings/arm/idle-states.txt > I thought I had given reviewed by to this. Or may be I confused you giving the big standard example that I want to add here. Anyways, Reviewed-by: Sudeep Holla <sudeep.holla@xxxxxxx> -- Regards, Sudeep
