On Fri, Nov 15, 2019 at 3:07 AM Taniya Das <tdas@xxxxxxxxxxxxxx> wrote:
>
> The GPUCC clock provider have a bunch of generic properties that
> are needed in a device tree. Add a YAML schemas for those.
>
> Signed-off-by: Taniya Das <tdas@xxxxxxxxxxxxxx>
> ---
> .../devicetree/bindings/clock/qcom,gpucc.txt | 24 --------
> .../devicetree/bindings/clock/qcom,gpucc.yaml | 69 ++++++++++++++++++++++
> 2 files changed, 69 insertions(+), 24 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.txt
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
> deleted file mode 100644
> index 269afe8a..0000000
> --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
> +++ /dev/null
> @@ -1,24 +0,0 @@
> -Qualcomm Graphics Clock & Reset Controller Binding
> ---------------------------------------------------
> -
> -Required properties :
> -- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"
> -- reg : shall contain base register location and length
> -- #clock-cells : from common clock binding, shall contain 1
> -- #reset-cells : from common reset binding, shall contain 1
> -- #power-domain-cells : from generic power domain binding, shall contain 1
> -- clocks : shall contain the XO clock
> - shall contain the gpll0 out main clock (msm8998)
> -- clock-names : shall be "xo"
> - shall be "gpll0" (msm8998)
> -
> -Example:
> - gpucc: clock-controller@5090000 {
> - compatible = "qcom,sdm845-gpucc";
> - reg = <0x5090000 0x9000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #power-domain-cells = <1>;
> - clocks = <&rpmhcc RPMH_CXO_CLK>;
> - clock-names = "xo";
> - };
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> new file mode 100644
> index 0000000..c2d6243
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
> @@ -0,0 +1,69 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Graphics Clock & Reset Controller Binding
> +
> +maintainers:
> + - Taniya Das <tdas@xxxxxxxxxxxxxx>
> +
> +description: |
> + Qualcomm grpahics clock control module which supports the clocks, resets and
> + power domains.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,msm8998-gpucc
> + - qcom,sdm845-gpucc
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> + items:
> + - description: Board XO source
> + - description: GPLL0 source from GCC
This is not an accurate conversion. GPLL0 was not valid for 845, and
is required for 8998.
> +
> + clock-names:
> + minItems: 1
> + maxItems: 2
> + items:
> + - const: xo
> + - const: gpll0
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + '#power-domain-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> + - '#reset-cells'
> + - '#power-domain-cells'
> +
> +examples:
> + # Example of GPUCC with clock node properties for SDM845:
> + - |
> + clock-controller@5090000 {
> + compatible = "qcom,sdm845-gpucc";
> + reg = <0x5090000 0x9000>;
> + clocks = <&rpmhcc 0>, <&gcc 32>;
> + clock-names = "xo", "gpll0";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +...
> --
> Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
> of the Code Aurora Forum, hosted by the Linux Foundation.
>
