On 27-10-19, 14:25, Stephen Boyd wrote:
> Quoting Vinod Koul (2019-10-21 03:54:35)
> > On 17-10-19, 10:48, Stephen Boyd wrote:
> > > > > > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> > > > > > index 12ca2d14797f..13d4d14a5744 100644
> > > > > > --- a/drivers/clk/qcom/gcc-sm8150.c
> > > > > > +++ b/drivers/clk/qcom/gcc-sm8150.c
> > > > > > @@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
> > > > > > },
> > > > > > };
> > > > > >
> > > > > > +static struct clk_branch gcc_gpu_gpll0_clk_src = {
> > > > > > + .halt_check = BRANCH_HALT_SKIP,
> > > > >
> > > > > Why skip?
> > > >
> > > > I will explore and add comments for that
> > > >
> > > > > > + .clkr = {
> > > > > > + .enable_reg = 0x52004,
> > > > > > + .enable_mask = BIT(15),
> > > > > > + .hw.init = &(struct clk_init_data){
> > > > > > + .name = "gcc_gpu_gpll0_clk_src",
> > > > > > + .parent_hws = (const struct clk_hw *[]){
> > > > > > + &gpll0.clkr.hw },
> > > > > > + .num_parents = 1,
> > > > > > + .flags = CLK_SET_RATE_PARENT,
> > > > > > + .ops = &clk_branch2_ops,
> > > > > > + },
> > > > > > + },
> > > > > > +};
> > > > > > +
> > > > > > +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
> > > > > > + .halt_check = BRANCH_HALT_SKIP,
> > > > >
> > > > > Why skip?
> > > > >
> > >
> > > Any answer from the explorations?
> >
> > Yeah so asking around the answer I got is that these are external
> > clocks and we need cannot rely on CLK_OFF bit for these clocks
> >
>
> The parents are from some other clk controller? Not external to the
> chip, right? If so, I still don't get it. Please add some sort of
> comment here in the code.
Yeah I have added a comment and posted v2 few days back.
Thanks
--
~Vinod
