On Thu, Oct 10, 2019 at 01:39:26PM +0200, Ulf Hansson wrote:
> Update PSCI DT bindings to allow to represent idle states for CPUs and the
> CPU topology, by using a hierarchical layout. Primarily this is done by
> re-using the existing power domain description [1] and the domain idle
> state description [2].
>
> Let's also take the opportunity to update the examples to clarify the
> difference between the currently supported flattened layout vs the new
> hierarchical layout.
>
This looks fine to me. FWIW:
Reviewed-by: Sudeep Holla <sudeep.holla@xxxxxxx>
But before this gets merged, I would like to add another but "the golden"
example Qcom *always* referred during ACPI LPI discussions. Ofcourse, it
can be addition patch and if I get time, I can write this but no promise
ATM.
Hierarchical Representation:
System
1. SYSTEM_RET
2. SYSTEM_PG
Cluster#0
1. CLUSTER_RET
2. CLUSTER_PG
Core#0
1. CORE_CG
2. CORE_RET
3. CORE_PG
Core#1
1. CORE_CG
2. CORE_RET
3. CORE_PG
Cluster#1 (ditto)
Flattened Representation:
Core#0
1 CORE_CG
2 CORE_RET
3 CORE_RET + CLUSTER_RET
4 CORE_RET + CLUSTER_RET + SYSTEM_RET
5 CORE_PG
6 CORE_PG + CLUSTER_RET
7 CORE_PG + CLUSTER_RET + SYSTEM_RET
8 CORE_PG + CLUSTER_PG
9 CORE_PG + CLUSTER_PG + SYSTEM_RET
10 CORE_PG + CLUSTER_PG + SYSTEM_PG
Though we may not implement everything needed to support this, but
we must ensure we don't have to end up in a situation breaking backward
compatibility trying to support the same.
--
Regards,
Sudeep
