Quoting Brian Masney (2019-10-05 18:01:00)
> From: Jonathan Marek <jonathan@xxxxxxxx>
>
> Add frequency table for the gfx3d clock that's needed in order to
> support the GPU upstream on msm8974-based systems.
>
> Signed-off-by: Jonathan Marek <jonathan@xxxxxxxx>
> Signed-off-by: Brian Masney <masneyb@xxxxxxxxxxxxx>
> ---
> drivers/clk/qcom/mmcc-msm8974.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
> index bcb0a397ef91..e70abfe2a792 100644
> --- a/drivers/clk/qcom/mmcc-msm8974.c
> +++ b/drivers/clk/qcom/mmcc-msm8974.c
> @@ -452,10 +452,17 @@ static struct clk_rcg2 mdp_clk_src = {
> },
> };
>
> +static struct freq_tbl ftbl_gfx3d_clk_src[] = {
> + F(37500000, P_GPLL0, 16, 0, 0),
> + F(533000000, P_MMPLL0, 1.5, 0, 0),
> + { }
> +};
On msm-3.10 kernel the gpu clk seems to be controlled by the RPM[1].
What is going on here? This code just looks wrong, but I think it was
added as an rcg so that the branch wasn't orphaned and would have some
sane frequency. Eventually we planned to parent it to a clk exposed in
the RPM clk driver. It's been a while so I'm having a hard time
remembering, but I think GPU clk on this device needed to be controlled
by RPM so that DDR self refresh wouldn't interact badly with ocmem? Or
maybe ocmem needed GPU to be enabled to work? Maybe there is some
information in the 3.10 downstream kernel.
> +
> static struct clk_rcg2 gfx3d_clk_src = {
> .cmd_rcgr = 0x4000,
> .hid_width = 5,
> .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
> + .freq_tbl = ftbl_gfx3d_clk_src,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gfx3d_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
[1] https://source.codeaurora.org/quic/la/kernel/msm-3.10/tree/arch/arm/mach-msm/clock-rpm-8974.c?h=msm-3.10#n82
