Quoting Vinod Koul (2019-06-08 02:14:36)
> On 07-06-19, 10:55, Stephen Boyd wrote:
> > Quoting Vinod Koul (2019-06-07 03:12:33)
>
> > > const struct clk_ops clk_alpha_pll_ops = {
> > > .enable = clk_alpha_pll_enable,
> > > .disable = clk_alpha_pll_disable,
> > > @@ -902,6 +1079,10 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
> > > ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
> > > if (ret)
> > > return ret;
> > > + ret = regmap_update_bits(regmap, PLL_MODE(pll),
> > > + PLL_BYPASSNL, PLL_BYPASSNL);
> > > + if (ret)
> > > + return ret;
> >
> > What is this?
>
> Sorry am not sure I understood the question. care to elaborate please?
The bypass bit of a PLL is very generic so I'm confused why the enable
function is only gaining this bit setting logic now. Plus, it's all
grouped together with the previous line so it looks like a possible
stray addition to the code? And after this there's an early exit from
the function if the PLL is already running, so we would put the PLL into
bypass and then return? What's going on here?
