[+Joerg on To:] On Mon, Jun 03, 2019 at 02:15:37PM +0200, Marc Gonzalez wrote: > From: Robin Murphy <robin.murphy@xxxxxxx> > > Apparently, some Qualcomm arm64 platforms which appear to expose their > SMMU global register space are still, in fact, using a hypervisor to > mediate it by trapping and emulating register accesses. Sadly, some > deployed versions of said trapping code have bugs wherein they go > horribly wrong for stores using r31 (i.e. XZR/WZR) as the source > register. > > While this can be mitigated for GCC today by tweaking the constraints > for the implementation of writel_relaxed(), to avoid any potential > arms race with future compilers more aggressively optimising register > allocation, the simple way is to just remove all the problematic > constant zeros. For the write-only TLB operations, the actual value is > irrelevant anyway and any old nearby variable will provide a suitable > GPR to encode. The one point at which we really do need a zero to clear > a context bank happens before any of the TLB maintenance where crashes > have been reported, so is apparently not a problem... :/ > > Reported-by: AngeloGioacchino Del Regno <kholk11@xxxxxxxxx> > Tested-by: Marc Gonzalez <marc.w.gonzalez@xxxxxxx> > Signed-off-by: Robin Murphy <robin.murphy@xxxxxxx> > Signed-off-by: Marc Gonzalez <marc.w.gonzalez@xxxxxxx> Acked-by: Will Deacon <will.deacon@xxxxxxx> Joerg -- Please can you take this as a fix for 5.2, with a Cc stable? Cheers, Will
