On Tue, 23 Apr 2019 at 13:13, Robin Murphy <robin.murphy@xxxxxxx> wrote:
>
> On 22/04/2019 08:10, Vivek Gautam wrote:
> > Bits[15:0] in CBFRSYNRA register contain information about
> > StreamID of the incoming transaction that generated the
> > fault. Dump CBFRSYNRA register to get this info.
> > This is specially useful in a distributed SMMU architecture
> > where multiple masters are connected to the SMMU.
> > SID information helps to quickly identify the faulting
> > master device.
> >
> > Signed-off-by: Vivek Gautam <vivek.gautam@xxxxxxxxxxxxxx>
> > Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> > ---
> >
> > Changes since v1:
> > - Addressed review comments, given by Bjorn, for nits.
> >
> > drivers/iommu/arm-smmu-regs.h | 2 ++
> > drivers/iommu/arm-smmu.c | 7 +++++--
> > 2 files changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h
> > index a1226e4ab5f8..e9132a926761 100644
> > --- a/drivers/iommu/arm-smmu-regs.h
> > +++ b/drivers/iommu/arm-smmu-regs.h
> > @@ -147,6 +147,8 @@ enum arm_smmu_s2cr_privcfg {
> > #define CBAR_IRPTNDX_SHIFT 24
> > #define CBAR_IRPTNDX_MASK 0xff
> >
> > +#define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2))
> > +
> > #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
> > #define CBA2R_RW64_32BIT (0 << 0)
> > #define CBA2R_RW64_64BIT (1 << 0)
> > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> > index 045d93884164..e000473f8205 100644
> > --- a/drivers/iommu/arm-smmu.c
> > +++ b/drivers/iommu/arm-smmu.c
> > @@ -575,7 +575,9 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
> > struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
> > struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
> > struct arm_smmu_device *smmu = smmu_domain->smmu;
> > + void __iomem *gr1_base = ARM_SMMU_GR1(smmu);
> > void __iomem *cb_base;
> > + u32 cbfrsynra;
>
> Nit: I would simply add to the existing "u32 fsr, fsynr;" declaration,
> but that's the sort of thing that could hopefully be fixed up when
> applying (or otherwise I might bulldoze it anyway in my eventual rework
> of register accesses throughout the driver). Regardless,
>
> Reviewed-by: Robin Murphy <robin.murphy@xxxxxxx>
>
> > cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
> > fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
> > @@ -585,10 +587,11 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
> >
> > fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
> > iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
> > + cbfrsynra = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
> >
> > dev_err_ratelimited(smmu->dev,
> > - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",
> > - fsr, iova, fsynr, cfg->cbndx);
> > + "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
> > + fsr, iova, fsynr, cbfrsynra, cfg->cbndx);
> >
> > writel(fsr, cb_base + ARM_SMMU_CB_FSR);
> > return IRQ_HANDLED;
> >
>
This is something I've had to hack up locally in the past, so
Acked-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx>
