On 25/03/2019 14:49, Marc Gonzalez wrote:
> See similar issue solved by commit 5f2420ed2189
> ("clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998")
>
> Without this patch, PCIe PHY init fails:
>
> qcom-qmp-phy 1c06000.phy: pipe_clk enable failed err=-16
> phy phy-1c06000.phy.0: phy init failed --> -16
>
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@xxxxxxx>
> ---
> drivers/clk/qcom/gcc-msm8998.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
> index c240fba794c7..033688264c7b 100644
> --- a/drivers/clk/qcom/gcc-msm8998.c
> +++ b/drivers/clk/qcom/gcc-msm8998.c
> @@ -2161,7 +2161,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
>
> static struct clk_branch gcc_pcie_0_pipe_clk = {
> .halt_reg = 0x6b018,
> - .halt_check = BRANCH_HALT,
> + .halt_check = BRANCH_HALT_SKIP,
> .clkr = {
> .enable_reg = 0x6b018,
> .enable_mask = BIT(0),
Bjorn, Jeffrey, et al,
Could someone review this patch and confirm it is required for functional PCIe?
Regards.
