On Wed, Feb 13, 2019 at 05:19:15PM -0800, Jeykumar Sankaran wrote:
> Iterate and assign HW intf block to physical encoders
> in encoder modeset. Moving all the HW block assignments
> to encoder modeset to allow easy switching to state
> based resource management.
>
> Signed-off-by: Jeykumar Sankaran <jsanka@xxxxxxxxxxxxxx>
Reviewed-by: Sean Paul <sean@xxxxxxxxxx>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 22 +++++++++++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 24 ----------------------
> 2 files changed, 21 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index f648e7f..98ea478 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -968,7 +968,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
> struct dpu_hw_mixer *hw_lm[MAX_CHANNELS_PER_ENC] = { NULL };
> int num_lm = 0, num_ctl = 0;
> - int i = 0, ret;
> + int i, j, ret;
>
> if (!drm_enc) {
> DPU_ERROR("invalid encoder\n");
> @@ -1065,6 +1065,26 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> phys->hw_pp = dpu_enc->hw_pp[i];
> phys->hw_ctl = hw_ctl[i];
>
> + dpu_rm_init_hw_iter(&hw_iter, drm_enc->base.id,
> + DPU_HW_BLK_INTF);
> + for (j = 0; j < MAX_CHANNELS_PER_ENC; j++) {
> + struct dpu_hw_intf *hw_intf;
> +
> + if (!dpu_rm_get_hw(&dpu_kms->rm, &hw_iter))
> + break;
> +
> + hw_intf = (struct dpu_hw_intf *)hw_iter.hw;
> + if (hw_intf->idx == phys->intf_idx)
> + phys->hw_intf = hw_intf;
> + }
> +
> + if (!phys->hw_intf) {
> + DPU_ERROR_ENC(dpu_enc,
> + "no intf block assigned at idx: %d\n",
> + i);
> + goto error;
> + }
> +
> phys->connector = conn->state->connector;
> if (phys->ops.mode_set)
> phys->ops.mode_set(phys, mode, adj_mode);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index ce65521..02362c5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -449,35 +449,11 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
>
> static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
> {
> - struct msm_drm_private *priv;
> - struct dpu_rm_hw_iter iter;
> struct dpu_hw_ctl *ctl;
> u32 flush_mask = 0;
>
> - if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev ||
> - !phys_enc->parent->dev->dev_private) {
> - DPU_ERROR("invalid encoder/device\n");
> - return;
> - }
> - priv = phys_enc->parent->dev->dev_private;
> -
> ctl = phys_enc->hw_ctl;
>
> - dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_INTF);
> - while (dpu_rm_get_hw(&phys_enc->dpu_kms->rm, &iter)) {
> - struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
> -
> - if (hw_intf->idx == phys_enc->intf_idx) {
> - phys_enc->hw_intf = hw_intf;
> - break;
> - }
> - }
> -
> - if (!phys_enc->hw_intf) {
> - DPU_ERROR("hw_intf not assigned\n");
> - return;
> - }
> -
> DPU_DEBUG_VIDENC(phys_enc, "\n");
>
> if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing))
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
