On Wed, Feb 27, 2019 at 10:06 AM Marc Gonzalez <marc.w.gonzalez@xxxxxxx> wrote:
>
> On 27/02/2019 08:00, Bjorn Andersson wrote:
>
> > SDM845 sports two PCIe controller/phy pairs; one GEN2 and one GEN3. Add
> > the nodes for the GEN2 pair.
> >
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> > ---
> >
> > Changes since v1:
> > - "reg" is spelled without a 't'
> >
> > arch/arm64/boot/dts/qcom/sdm845.dtsi | 103 +++++++++++++++++++++++++++
> > 1 file changed, 103 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index 5308f1671824..35887fedfd0e 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -1024,6 +1024,109 @@
> > };
> > };
> >
> > + pcie0: pci@1c00000 {
> > + compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
>
> $ git grep "qcom,pcie-sdm845\|qcom,sdm845-qmp-pcie-phy" drivers/
> /* Nada */
>
> Are you planning on landing more patches later?
> In particular, the PHY init sequence...
Have you seen
https://lore.kernel.org/lkml/20190226070125.22318-1-bjorn.andersson@xxxxxxxxxx/
?
