On 11/02/2019 14:59, Marc Zyngier wrote:
On 11/02/2019 14:29, AngeloGioacchino Del Regno wrote:
[...]
Also, just one more thing: yes this thing is going ARM64-wide and
- from my findings - it's targeting certain Qualcomm SoCs, but...
I'm not sure that only QC is affected by that, others may as well
have the same stupid bug.
At the moment, only QC SoCs seem to be affected, probably because
everyone else has debugged their hypervisor (or most likely doesn't
bother with shipping one).
In all honesty, we need some information from QC here: which SoCs are
affected, what is the exact nature of the bug, can it be triggered from
EL0. Randomly papering over symptoms is not something I really like
doing, and is likely to generate problems on unaffected systems.
And even if we *were* to just try papering over the observed extent of
the issue, I'd still be inclined to confine it to arm-smmu.c where the
impact is finite and minimal - of the 4 instances of writel(0) there, 3
of them don't care what the data is (so could just reuse the base
register or similar) and the other one already has a zero in a GPR to
hand by construction.
Robin.
