On Fri, Jan 25, 2019 at 03:45:03PM -0800, Bjorn Andersson wrote:
> Enabling PCIe requires several of the PCIe related resets from GCC, so
> add them all.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> ---
>
> Stephen, I suggest that we merge this patch through Andy's devicetree branch,
> together with the DT patch in the end of this series.
>
> drivers/clk/qcom/gcc-qcs404.c | 7 +++++++
> include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
> index 64da032bb9ed..cfb8789ff706 100644
> --- a/drivers/clk/qcom/gcc-qcs404.c
> +++ b/drivers/clk/qcom/gcc-qcs404.c
> @@ -2675,6 +2675,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
> [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
> [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
> [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
> + [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = {0x3e040, 6},
> + [GCC_PCIE_0_AHB_ARES] = {0x3e040, 5},
> + [GCC_PCIE_0_AXI_SLAVE_ARES] = {0x3e040, 4},
> + [GCC_PCIE_0_AXI_MASTER_ARES] = {0x3e040, 3},
> + [GCC_PCIE_0_CORE_STICKY_ARES] = {0x3e040, 2},
> + [GCC_PCIE_0_SLEEP_ARES] = {0x3e040, 1},
> + [GCC_PCIE_0_PIPE_ARES] = {0x3e040, 0},
Hello Bjorn,
please add spaces before and after the braces, to match the
syntax of the existing lines.
With that,
Reviewed-by: Niklas Cassel <niklas.cassel@xxxxxxxxxx>
Kind regards,
Niklas
> [GCC_EMAC_BCR] = { 0x4e000 },
> };
>
> diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> index 6ceb55ed72c6..00ab0d77b38a 100644
> --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
> +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> @@ -161,5 +161,12 @@
> #define GCC_PCIE_0_LINK_DOWN_BCR 11
> #define GCC_PCIEPHY_0_PHY_BCR 12
> #define GCC_EMAC_BCR 13
> +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14
> +#define GCC_PCIE_0_AHB_ARES 15
> +#define GCC_PCIE_0_AXI_SLAVE_ARES 16
> +#define GCC_PCIE_0_AXI_MASTER_ARES 17
> +#define GCC_PCIE_0_CORE_STICKY_ARES 18
> +#define GCC_PCIE_0_SLEEP_ARES 19
> +#define GCC_PCIE_0_PIPE_ARES 20
>
> #endif
> --
> 2.18.0
>
