On Fri, Dec 28 2018 at 17:07 -0700, Rob Herring wrote:
On Wed, Dec 19, 2018 at 03:11:02PM -0700, Lina Iyer wrote:
SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
routed to the PDC as interrupts that can be used to wake the system up
from deep low power modes and suspend.
Cc: devicetree@xxxxxxxxxxxxxxx
Signed-off-by: Lina Iyer <ilina@xxxxxxxxxxxxxx>
---
.../devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
index 665aadb5ea28..a522ca46667d 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
@@ -29,6 +29,11 @@ SDM845 platform.
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
+- wakeup-parent:
+ Usage: optional
+ Value type: <phandle>
+ Definition: A phandle to the wakeup interrupt controller for the SoC.
Is this really necessary? Is there more than one possible wakeup-parent
node?
No. There is only one but depending on the architecture, the wakeup
interrupt controller could be different device like PDC on SDM845 or MPM
on SDM820.
What do you have in mind? Let me know if you have a better idea than
referencing in DT.
Thanks,
Lina
+
- gpio-controller:
Usage: required
Value type: <none>
@@ -53,7 +58,6 @@ pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
-
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
@@ -160,6 +164,7 @@ Example:
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ wakeup-parent = <&pdc>;
qup9_active: qup9-active {
mux {
--
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