The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by
the phy during init. The clock needs to be enabled during the init
sequence, but may not be fully active until after the init sequence is
complete. This causes a catch-22 if the clock status is checked during
enable. As a result, skip the checks to avoid the troubling situation.
Signed-off-by: Jeffrey Hugo <jhugo@xxxxxxxxxxxxxx>
---
drivers/clk/qcom/gcc-msm8998.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 42de947..1a1806a 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -2496,7 +2496,7 @@ enum {
static struct clk_branch gcc_usb3_phy_pipe_clk = {
.halt_reg = 0x50004,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x50004,
.enable_mask = BIT(0),
--
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