On 04/12/2018 18:31, Jeffrey Hugo wrote:
> From what I can tell from the documentation, this is sourced from
> ufs_unipro_core_clk_src, which is inturn sourced from gpll0_out_main.
> I'm guessing gcc-msm8998.c needs to be updated to reflect this. It
> would also be good to check this against the downstream kernel.
With Stephen's "define xo clock" patch applied:
# cat clk_summary
enable prepare protect duty
clock count count count rate accuracy phase cycle
---------------------------------------------------------------------------------------------
gcc_usb_phy_cfg_ahb2phy_clk 0 0 0 0 0 0 50000
gcc_usb3_phy_pipe_clk 0 0 0 0 0 0 50000
gcc_usb30_sleep_clk 0 0 0 0 0 0 50000
gcc_ufs_tx_symbol_0_clk 0 0 0 0 0 0 50000
gcc_ufs_rx_symbol_1_clk 0 0 0 0 0 0 50000
gcc_ufs_rx_symbol_0_clk 0 0 0 0 0 0 50000
gcc_ufs_phy_aux_clk 0 0 0 0 0 0 50000
gcc_ufs_ice_core_clk 0 0 0 0 0 0 50000
gcc_ufs_ahb_clk 0 0 0 0 0 0 50000
gcc_tsif_inactivity_timers_clk 0 0 0 0 0 0 50000
gcc_tsif_ahb_clk 0 0 0 0 0 0 50000
gcc_sdcc4_ahb_clk 0 0 0 0 0 0 50000
gcc_sdcc2_ahb_clk 0 0 0 0 0 0 50000
gcc_prng_ahb_clk 0 0 0 0 0 0 50000
gcc_pdm_xo4_clk 0 0 0 0 0 0 50000
gcc_pdm_ahb_clk 0 0 0 0 0 0 50000
gcc_pcie_0_slv_axi_clk 0 0 0 0 0 0 50000
gcc_pcie_0_pipe_clk 0 0 0 0 0 0 50000
gcc_pcie_0_mstr_axi_clk 0 0 0 0 0 0 50000
gcc_pcie_0_cfg_ahb_clk 0 0 0 0 0 0 50000
gcc_mss_at_clk 0 0 0 0 0 0 50000
gcc_mmss_sys_noc_axi_clk 0 0 0 0 0 0 50000
gcc_mmss_qm_core_clk 0 0 0 0 0 0 50000
gcc_mmss_qm_ahb_clk 0 0 0 0 0 0 50000
gcc_mmss_noc_cfg_ahb_clk 0 0 0 0 0 0 50000
gcc_lpass_trig_clk 0 0 0 0 0 0 50000
gcc_lpass_at_clk 1 1 0 0 0 0 50000
gcc_hmss_trig_clk 0 0 0 0 0 0 50000
gcc_hmss_dvm_bus_clk 1 1 0 0 0 0 50000
gcc_hmss_at_clk 0 0 0 0 0 0 50000
gcc_gpu_snoc_dvm_gfx_clk 0 0 0 0 0 0 50000
gcc_gpu_cfg_ahb_clk 0 0 0 0 0 0 50000
gcc_gpu_bimc_gfx_src_clk 0 0 0 0 0 0 50000
gcc_gpu_bimc_gfx_clk 0 0 0 0 0 0 50000
gcc_blsp2_sleep_clk 0 0 0 0 0 0 50000
gcc_blsp2_ahb_clk 3 3 0 0 0 0 50000
gcc_blsp1_sleep_clk 0 0 0 0 0 0 50000
gcc_blsp1_ahb_clk 0 0 0 0 0 0 50000
gcc_bimc_mss_q6_axi_clk 0 0 0 0 0 0 50000
gcc_bimc_hmss_axi_clk 0 0 0 0 0 0 50000
gcc_apss_qdss_tsctr_div8_clk 0 0 0 0 0 0 50000
gcc_apss_qdss_tsctr_div2_clk 0 0 0 0 0 0 50000
gcc_aggre1_noc_xo_clk 0 0 0 0 0 0 50000
sleep_clk 0 0 0 32764 0 0 50000
xo_board 1 1 0 19200000 0 0 50000
ln_bb_a_clk1 0 0 0 19200000 0 0 50000
ln_bb_clk1 0 0 0 19200000 0 0 50000
xo 1 1 0 19200000 0 0 50000
gcc_rx1_usb2_clkref_clk 0 0 0 19200000 0 0 50000
gcc_pcie_clkref_clk 0 0 0 19200000 0 0 50000
gcc_ufs_clkref_clk 0 0 0 19200000 0 0 50000
gcc_hdmi_clkref_clk 0 0 0 19200000 0 0 50000
gcc_usb3_clkref_clk 0 0 0 19200000 0 0 50000
usb3_phy_aux_clk_src 0 0 0 1200000 0 0 50000
gcc_usb3_phy_aux_clk 0 0 0 1200000 0 0 50000
usb30_mock_utmi_clk_src 0 0 0 19200000 0 0 50000
gcc_usb30_mock_utmi_clk 0 0 0 19200000 0 0 50000
tsif_ref_clk_src 0 0 0 19200000 0 0 50000
gcc_tsif_ref_clk 0 0 0 19200000 0 0 50000
sdcc4_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_sdcc4_apps_clk 0 0 0 19200000 0 0 50000
sdcc2_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_sdcc2_apps_clk 0 0 0 19200000 0 0 50000
pdm2_clk_src 0 0 0 19200000 0 0 50000
gcc_pdm2_clk 0 0 0 19200000 0 0 50000
pcie_aux_clk_src 0 0 0 19200000 0 0 50000
gcc_pcie_0_aux_clk 0 0 0 19200000 0 0 50000
gcc_pcie_phy_aux_clk 0 0 0 19200000 0 0 50000
hmss_rbcpr_clk_src 0 0 0 19200000 0 0 50000
gcc_hmss_rbcpr_clk 0 0 0 19200000 0 0 50000
hmss_ahb_clk_src 0 0 0 19200000 0 0 50000
gcc_hmss_ahb_clk 0 0 0 19200000 0 0 50000
gpll4 0 0 0 384000000 0 0 50000
gpll4_out_test 0 0 0 384000000 0 0 50000
gpll4_out_odd 0 0 0 384000000 0 0 50000
gpll4_out_main 0 0 0 384000000 0 0 50000
gpll4_out_even 0 0 0 384000000 0 0 50000
gpll3 0 0 0 921600000 0 0 50000
gpll3_out_test 0 0 0 921600000 0 0 50000
gpll3_out_odd 0 0 0 921600000 0 0 50000
gpll3_out_main 0 0 0 921600000 0 0 50000
gpll3_out_even 0 0 0 921600000 0 0 50000
gpll2 0 0 0 1286400000 0 0 50000
gpll2_out_test 0 0 0 1286400000 0 0 50000
gpll2_out_odd 0 0 0 1286400000 0 0 50000
gpll2_out_main 0 0 0 1286400000 0 0 50000
gpll2_out_even 0 0 0 1286400000 0 0 50000
gpll1 0 0 0 1056000000 0 0 50000
gpll1_out_test 0 0 0 1056000000 0 0 50000
gpll1_out_odd 0 0 0 1056000000 0 0 50000
gpll1_out_main 0 0 0 1056000000 0 0 50000
gpll1_out_even 0 0 0 1056000000 0 0 50000
gpll0 0 0 0 595200000 0 0 50000
gpll0_out_test 0 0 0 595200000 0 0 50000
gpll0_out_odd 0 0 0 595200000 0 0 50000
gpll0_out_main 0 0 0 595200000 0 0 50000
ufs_unipro_core_clk_src 0 0 0 148800000 0 0 50000
gcc_ufs_unipro_core_clk 0 0 0 148800000 0 0 50000
usb30_master_clk_src 0 0 0 119040000 0 0 50000
gcc_aggre1_usb3_axi_clk 0 0 0 119040000 0 0 50000
gcc_cfg_noc_usb3_axi_clk 0 0 0 119040000 0 0 50000
gcc_usb30_master_clk 0 0 0 119040000 0 0 50000
ufs_axi_clk_src 0 0 0 198400000 0 0 50000
gcc_aggre1_ufs_axi_clk 0 0 0 198400000 0 0 50000
gcc_ufs_axi_clk 0 0 0 198400000 0 0 50000
gpll0_out_even 0 0 0 595200000 0 0 50000
gp3_clk_src 0 0 0 19200000 0 0 50000
gcc_gp3_clk 0 0 0 19200000 0 0 50000
gp2_clk_src 0 0 0 19200000 0 0 50000
gcc_gp2_clk 0 0 0 19200000 0 0 50000
gp1_clk_src 0 0 0 19200000 0 0 50000
gcc_gp1_clk 0 0 0 19200000 0 0 50000
blsp2_uart3_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_uart3_apps_clk 0 0 0 19200000 0 0 50000
blsp2_uart2_apps_clk_src 1 1 0 1843200 0 0 50000
gcc_blsp2_uart2_apps_clk 3 3 0 1843200 0 0 50000
blsp2_uart1_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_uart1_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup6_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup6_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup6_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup6_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup5_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup5_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup5_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup5_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup4_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup4_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup4_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup4_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup3_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup3_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup3_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup3_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup2_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup2_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup2_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup2_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup1_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup1_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp2_qup1_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp2_qup1_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp1_uart3_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_uart3_apps_clk 0 0 0 19200000 0 0 50000
blsp1_uart2_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_uart2_apps_clk 0 0 0 19200000 0 0 50000
blsp1_uart1_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_uart1_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup6_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup6_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup6_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup6_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup5_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup5_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup5_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup5_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup4_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup4_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup4_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup4_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup3_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup3_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup3_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup3_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup2_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup2_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup2_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup2_i2c_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup1_spi_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup1_spi_apps_clk 0 0 0 19200000 0 0 50000
blsp1_qup1_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
gcc_blsp1_qup1_i2c_apps_clk 0 0 0 19200000 0 0 50000
# grep ufs clk_summary
gcc_ufs_tx_symbol_0_clk 0 0 0 0 0 0 50000
gcc_ufs_rx_symbol_1_clk 0 0 0 0 0 0 50000
gcc_ufs_rx_symbol_0_clk 0 0 0 0 0 0 50000
gcc_ufs_phy_aux_clk 0 0 0 0 0 0 50000
gcc_ufs_ice_core_clk 0 0 0 0 0 0 50000
gcc_ufs_ahb_clk 0 0 0 0 0 0 50000
gcc_ufs_clkref_clk 0 0 0 19200000 0 0 50000
ufs_unipro_core_clk_src 0 0 0 148800000 0 0 50000
gcc_ufs_unipro_core_clk 0 0 0 148800000 0 0 50000
ufs_axi_clk_src 0 0 0 198400000 0 0 50000
gcc_aggre1_ufs_axi_clk 0 0 0 198400000 0 0 50000
gcc_ufs_axi_clk 0 0 0 198400000 0 0 50000
I find it surprising that many ufs-related clocks are unparented,
have no rate, and have never been enabled. But that's probably
a red-herring. As Bjorn mentioned, the bootloader probably leaves
all the UFS clocks in the correct state, so the problem must be
elsewhere... Will check the init sequence.
Just for completeness sake, here are the clock parents downstream:
CLOCK=gcc_ufs_ahb_clk PARENT=None
CLOCK=gcc_ufs_clkref_clk PARENT=None
CLOCK=gcc_ufs_rx_symbol_0_clk PARENT=None
CLOCK=gcc_ufs_rx_symbol_1_clk PARENT=None
CLOCK=gcc_ufs_tx_symbol_0_clk PARENT=None
CLOCK=gcc_aggre1_ufs_axi_clk PARENT=ufs_axi_clk_src
CLOCK=gcc_aggre1_ufs_axi_hw_ctl_clk PARENT=gcc_aggre1_ufs_axi_clk
CLOCK=gcc_ufs_axi_clk PARENT=ufs_axi_clk_src
CLOCK=gcc_ufs_axi_hw_ctl_clk PARENT=gcc_ufs_axi_clk
CLOCK=gcc_ufs_ice_core_clk PARENT=ufs_ice_core_clk_src
CLOCK=gcc_ufs_ice_core_hw_ctl_clk PARENT=gcc_ufs_ice_core_clk
CLOCK=gcc_ufs_phy_aux_clk PARENT=ufs_phy_aux_clk_src
CLOCK=gcc_ufs_phy_aux_hw_ctl_clk PARENT=gcc_ufs_phy_aux_clk
CLOCK=gcc_ufs_unipro_core_clk PARENT=ufs_unipro_core_clk_src
CLOCK=gcc_ufs_unipro_core_hw_ctl_clk PARENT=gcc_ufs_unipro_core_clk
CLOCK=ufs_axi_clk_src PARENT=gpll0_out_main
CLOCK=ufs_ice_core_clk_src PARENT=gpll0_out_main
CLOCK=ufs_phy_aux_clk_src PARENT=cxo_clk_src
CLOCK=ufs_unipro_core_clk_src PARENT=gpll0_out_main
Regards.
